Cadence USB3 bindings specify a specific reg order. Adjust DT entries
to match the bindings.
Signed-off-by: Alexander Stein <alexander.stein@xxxxxxxxxxxxxxx>
---
arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi | 10 ++++------
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
index e62a43591361..fc1a5d34382b 100644
--- a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
@@ -157,12 +157,10 @@ usbotg3: usb@5b110000 {
usbotg3_cdns3: usb@5b120000 {
compatible = "cdns,usb3";
- reg = <0x5b130000 0x10000>, /* memory area for HOST registers */
- <0x5b140000 0x10000>, /* memory area for DEVICE registers */
- <0x5b120000 0x10000>; /* memory area for OTG/DRD registers */
- reg-names = "xhci", "dev", "otg";
- #address-cells = <1>;
- #size-cells = <1>;
+ reg = <0x5b120000 0x10000>, /* memory area for OTG/DRD registers */
+ <0x5b130000 0x10000>, /* memory area for HOST registers */
+ <0x5b140000 0x10000>; /* memory area for DEVICE registers */
+ reg-names = "otg", "xhci", "dev";
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
--
2.34.1
