On 21/07/2023 10:38, Meng Li wrote:
> Intel Stratix10 is very the same with Agilex platform, the DWC2 IP on
> the Stratix platform also does not support clock-gating. The commit
> 3d8d3504d233("usb: dwc2: Add platform specific data for Intel's Agilex")
> had fixed this issue. So, add the essential compatible to also use the
> specific data on Stratix10 platform.
>
> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx>
>From where did you get it?
Did you just fake a tag to pass the review?
> Signed-off-by: Meng Li <Meng.Li@xxxxxxxxxxxxx>
> ---
>
> v2:
> - Add SoC specific compatible as per Krzysztof comment
>
> ---
> arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
> index 41c9eb51d0ee..46691e72f46b 100644
> --- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
> +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
> @@ -491,7 +491,7 @@ usbphy0: usbphy@0 {
> };
>
> usb0: usb@ffb00000 {
> - compatible = "snps,dwc2";
> + compatible = "intel,socfpga-stratix10-hsotg", "intel,socfpga-agilex-hsotg", "snps,dwc2";
It does not look like you tested the DTS against bindings. Please run
`make dtbs_check` (see
Documentation/devicetree/bindings/writing-schema.rst or
https://www.linaro.org/blog/tips-and-tricks-for-validating-devicetree-sources-with-the-devicetree-schema/
for instructions).
Best regards,
Krzysztof
