Add PLDA XpressRICH host controller dt-bindings. Both Microchip PolarFire SoC and StarFive JH7110 SoC are using PLDA XpressRICH PCIe host controller IP. Signed-off-by: Minda Chen <minda.chen@xxxxxxxxxxxxxxxx> Reviewed-by: Hal Feng <hal.feng@xxxxxxxxxxxxxxxx> --- .../pci/plda,xpressrich-pcie-host.yaml | 66 +++++++++++++++++++ 1 file changed, 66 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/plda,xpressrich-pcie-host.yaml diff --git a/Documentation/devicetree/bindings/pci/plda,xpressrich-pcie-host.yaml b/Documentation/devicetree/bindings/pci/plda,xpressrich-pcie-host.yaml new file mode 100644 index 000000000000..10a10862a078 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/plda,xpressrich-pcie-host.yaml @@ -0,0 +1,66 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/plda,xpressrich-pcie-host.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: PLDA XpressRICH PCIe host controller + +maintainers: + - Daire McNamara <daire.mcnamara@xxxxxxxxxxxxx> + - Minda Chen <minda.chen@xxxxxxxxxxxxxxxx> + +allOf: + - $ref: /schemas/pci/pci-bus.yaml# + - $ref: plda,xpressrich-pcie-common.yaml# + - $ref: /schemas/interrupt-controller/msi-controller.yaml# + +properties: + compatible: + const: plda,xpressrich-pcie-host + +required: + - compatible + - reg + - reg-names + - "#interrupt-cells" + - interrupts + - interrupt-map-mask + - interrupt-map + - msi-controller + +unevaluatedProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + pcie0: pcie@12000000 { + compatible = "plda,xpressrich-pcie-host"; + reg = <0x0 0x12000000 0x0 0x00010000>, + <0x0 0x43000000 0x0 0x00010000>; + reg-names = "host", "cfg"; + ranges = <0x03000000 0x0 0x88000000 0x0 0x88000000 0x0 0x04000000>; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + interrupts = <131>; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0 0 0 1 &pcie_intc0 0>, + <0 0 0 2 &pcie_intc0 1>, + <0 0 0 3 &pcie_intc0 2>, + <0 0 0 4 &pcie_intc0 3>; + interrupt-parent = <&plic0>; + msi-parent = <&pcie0>; + msi-controller; + bus-range = <0x00 0x7f>; + + pcie_intc0: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + }; -- 2.17.1
