On 19/07/2023 04:55, Meng Li wrote:
> Intel Stratix10 is very the same with Agilex platform, the DWC2 IP on
> the Stratix platform also does not support clock-gating. So, refer to
> commit 3d8d3504d233("usb: dwc2: Add platform specific data for
> Intel's Agilex"), add platform specific data for Intel Stratix10 platform.
>
> Signed-off-by: Meng Li <Meng.Li@xxxxxxxxxxxxx>
> ---
> drivers/usb/dwc2/params.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/usb/dwc2/params.c b/drivers/usb/dwc2/params.c
> index 8eab5f38b110..3d085ae1ecd8 100644
> --- a/drivers/usb/dwc2/params.c
> +++ b/drivers/usb/dwc2/params.c
> @@ -267,6 +267,8 @@ const struct of_device_id dwc2_of_match_table[] = {
> .data = dwc2_set_stm32mp15_hsotg_params },
> { .compatible = "intel,socfpga-agilex-hsotg",
> .data = dwc2_set_socfpga_agilex_params },
> + { .compatible = "intel,socfpga-stratix10-hsotg",
> + .data = dwc2_set_socfpga_agilex_params },
NAK. I already wrote why.
Best regards,
Krzysztof
