On 18/07/2023 05:08, Meng Li wrote:
> Intel Stratix10 is very the same with Agilex platform, the DWC2 IP on
> the Stratix platform also does not support clock-gating. The commit
> 3d8d3504d233("usb: dwc2: Add platform specific data for Intel's Agilex")
> had fixed this issue. So, add the essential compatible to also use the
> specific data on Stratix10 platform.
>
> Signed-off-by: Meng Li <Meng.Li@xxxxxxxxxxxxx>
> ---
> arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
> index ea788a920eab..b8dd5509c214 100644
> --- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
> +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
> @@ -490,7 +490,7 @@ usbphy0: usbphy@0 {
> };
>
> usb0: usb@ffb00000 {
> - compatible = "snps,dwc2";
> + compatible = "intel,socfpga-agilex-hsotg", "snps,dwc2";
You miss SoC specific compatible.
Best regards,
Krzysztof
