Re: [PATCH v7 2/2] EDAC/versal: Add a Xilinx Versal memory controller driver

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On Mon, Jul 17, 2023 at 12:31:09PM +0000, Datta, Shubhrajyoti wrote:
> We disable all the interrupts and enable only the correctable and
> non-correctable errors. The disable takes care of the issue that if
> other interrupts are enabled then there is no one to handle the
> interrupts.

What if someone else has enabled an interrupt line for them and you
disable it?

That doesn't make any sense.

> Also the enable interrupts are needed for the driver to work. The
> debug for error injection to test the notification.

The fact that it is not obvious why you're toggling the interrupts there
means you need a big fat comment explaining what you're doing.

Thx.

-- 
Regards/Gruss,
    Boris.

https://people.kernel.org/tglx/notes-about-netiquette



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