On 2023/7/13 22:57, Rob Herring wrote: > On Thu, Jul 13, 2023 at 02:39:19PM +0200, Krzysztof Kozlowski wrote: >> On 13/07/2023 14:28, Mark Brown wrote: >> > On Thu, Jul 13, 2023 at 05:00:14PM +0800, William Qiu wrote: >> > >> >> The SPI controller only need apb_pclk clock to work properly on JH7110 SoC, >> >> so there add minItems whose value is equal to 1. Other platforms do not >> >> have this constraint. >> > >> > Presumably this means that this is some variant of the usual pl022 IP, >> >> Hm, in such case this could mean we need dedicated compatible. > > Except the vendor in the ID registers should be different if the IP is > modified. > > I suspect that PCLK and SSPCLK are tied to the same clock source. There > must be an SSPCLK because that is the one used to clock the SPI bus and > we need to know the frequency of it. > > Rob After communicating with colleagues in SoC FE, I learned that PCLK and SSPCLK were homologous on JH7110. He said that SSPCLK would divide the frequency internally anyway, and there was no need for external part frequency, so he directly gave them together. So, should I call this clock ssp_apb or keep it SSPCLK? Best regards, William
