On Tue, 4 Jul 2023 at 08:49, Xingyu Wu <xingyu.wu@xxxxxxxxxxxxxxxx> wrote:
>
> Add PLL clocks input from PLL clocks driver in SYSCRG node.
>
> Reviewed-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx>
> Signed-off-by: Xingyu Wu <xingyu.wu@xxxxxxxxxxxxxxxx>
> ---
> arch/riscv/boot/dts/starfive/jh7110.dtsi | 8 ++++++--
> 1 file changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> index 11dd4c9d64b0..cdfd036a0e6c 100644
> --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
> +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> @@ -452,12 +452,16 @@ syscrg: clock-controller@13020000 {
> <&gmac1_rgmii_rxin>,
> <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
> <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
> - <&tdm_ext>, <&mclk_ext>;
> + <&tdm_ext>, <&mclk_ext>,
> + <&pllclk JH7110_CLK_PLL0_OUT>,
> + <&pllclk JH7110_CLK_PLL1_OUT>,
> + <&pllclk JH7110_CLK_PLL2_OUT>;
Once these are updated to <&pll ?> or <&pllclk JH7110_PLLCLK_PLL?_OUT>
if you still want to keep the defines:
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@xxxxxxxxxxxxx>
> clock-names = "osc", "gmac1_rmii_refin",
> "gmac1_rgmii_rxin",
> "i2stx_bclk_ext", "i2stx_lrck_ext",
> "i2srx_bclk_ext", "i2srx_lrck_ext",
> - "tdm_ext", "mclk_ext";
> + "tdm_ext", "mclk_ext",
> + "pll0_out", "pll1_out", "pll2_out";
> #clock-cells = <1>;
> #reset-cells = <1>;
> };
> --
> 2.25.1
>
