On Wed, 12 Jul 2023 at 11:22, Xingyu Wu <xingyu.wu@xxxxxxxxxxxxxxxx> wrote:
>
> Add STGCRG/ISPCRG/VOUTCRG new node to support JH7110
> System-Top-Group, Image-Signal-Process and Video-Output
> clock and reset drivers for the JH7110 RISC-V SoC.
>
> Reviewed-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx>
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@xxxxxxxxxxxxx>
> Signed-off-by: Xingyu Wu <xingyu.wu@xxxxxxxxxxxxxxxx>
> ---
> arch/riscv/boot/dts/starfive/jh7110.dtsi | 55 ++++++++++++++++++++++++
> 1 file changed, 55 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> index e9c1e4ad71a2..0005fa163a78 100644
> --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
> +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> @@ -6,6 +6,7 @@
>
> /dts-v1/;
> #include <dt-bindings/clock/starfive,jh7110-crg.h>
> +#include <dt-bindings/power/starfive,jh7110-pmu.h>
> #include <dt-bindings/reset/starfive,jh7110-crg.h>
>
> / {
> @@ -398,6 +399,25 @@ i2c2: i2c@10050000 {
> status = "disabled";
> };
>
> + stgcrg: clock-controller@10230000 {
> + compatible = "starfive,jh7110-stgcrg";
> + reg = <0x0 0x10230000 0x0 0x10000>;
> + clocks = <&osc>,
> + <&syscrg JH7110_SYSCLK_HIFI4_CORE>,
> + <&syscrg JH7110_SYSCLK_STG_AXIAHB>,
> + <&syscrg JH7110_SYSCLK_USB_125M>,
> + <&syscrg JH7110_SYSCLK_CPU_BUS>,
> + <&syscrg JH7110_SYSCLK_HIFI4_AXI>,
> + <&syscrg JH7110_SYSCLK_NOCSTG_BUS>,
> + <&syscrg JH7110_SYSCLK_APB_BUS>;
> + clock-names = "osc", "hifi4_core",
> + "stg_axiahb", "usb_125m",
> + "cpu_bus", "hifi4_axi",
> + "nocstg_bus", "apb_bus";
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + };
> +
> uart3: serial@12000000 {
> compatible = "snps,dw-apb-uart";
> reg = <0x0 0x12000000 0x0 0x10000>;
> @@ -558,5 +578,40 @@ pwrc: power-controller@17030000 {
> interrupts = <111>;
> #power-domain-cells = <1>;
> };
> +
> + ispcrg: clock-controller@19810000 {
> + compatible = "starfive,jh7110-ispcrg";
> + reg = <0x0 0x19810000 0x0 0x10000>;
> + clocks = <&syscrg JH7110_SYSCLK_ISP_TOP_CORE>,
> + <&syscrg JH7110_SYSCLK_ISP_TOP_AXI>,
> + <&syscrg JH7110_SYSCLK_NOC_BUS_ISP_AXI>,
> + <&dvp_clk>;
> + clock-names = "isp_top_core", "isp_top_axi",
> + "noc_bus_isp_axi", "dvp_clk";
> + resets = <&syscrg JH7110_SYSRST_ISP_TOP>,
> + <&syscrg JH7110_SYSRST_ISP_TOP_AXI>,
> + <&syscrg JH7110_SYSRST_NOC_BUS_ISP_AXI>;
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + power-domains = <&pwrc JH7110_PD_ISP>;
> + };
> +
> + voutcrg: clock-controller@295c0000 {
> + compatible = "starfive,jh7110-voutcrg";
> + reg = <0x0 0x295c0000 0x0 0x10000>;
> + clocks = <&syscrg JH7110_SYSCLK_VOUT_SRC>,
> + <&syscrg JH7110_SYSCLK_VOUT_TOP_AHB>,
> + <&syscrg JH7110_SYSCLK_VOUT_TOP_AXI>,
> + <&syscrg JH7110_SYSCLK_VOUT_TOP_HDMITX0_MCLK>,
> + <&syscrg JH7110_SYSCLK_I2STX0_BCLK>,
> + <&hdmitx0_pixelclk>;
> + clock-names = "vout_src", "vout_top_ahb",
> + "vout_top_axi", "vout_top_hdmitx0_mclk",
> + "i2stx0_bclk", "hdmitx0_pixelclk";
> + resets = <&syscrg JH7110_SYSRST_VOUT_TOP_SRC>;
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + power-domains = <&pwrc JH7110_PD_VOUT>;
> + };
> };
> };
> --
> 2.25.1
>
>
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