On Wed, Jul 12, 2023 at 09:50:37AM -0700, Palmer Dabbelt wrote: > On Wed, 12 Jul 2023 02:19:58 PDT (-0700), xingyu.wu@xxxxxxxxxxxxxxxx wrote: > > This patch serises are base on the basic JH7110 SYSCRG/AONCRG > > drivers and add new partial clock drivers and reset supports > > about System-Top-Group(STG), Image-Signal-Process(ISP) > > and Video-Output(VOUT) for the StarFive JH7110 RISC-V SoC. These > > clocks and resets could be used by DMA, VIN and Display modules. > Happy to take it through the RISC-V tree if folks want, but IMO it's > probably better aimed at the clock/reset folks. Either way I'd want to give > them a chance to ack/review it, so I'm going to drop it from my list. > > Acked-by: Palmer Dabbelt <palmer@xxxxxxxxxxxx> I had a look through it & I am generally happy with it - everything has either an R-b from DT folk or Hal on the drivers. I was going to propose the same thing as the PLL patchset - if Emil is happy with it, then I intend sending Stephen a PR for the drivers & bindings. Thanks, Conor.
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