Emil, On Tue, Jul 04, 2023 at 02:46:03PM +0800, Xingyu Wu wrote: > [Resending because it has a error about examples in syscon bingdings > and has to be fixed.] > > This patch serises are to add PLL clocks driver and providers by writing > and reading syscon registers for the StarFive JH7110 RISC-V SoC. And add > documentation and nodes to describe StarFive System Controller(syscon) > Registers. This patch serises are based on Linux 6.4. Could you take a look at this series when you get a chance, please? Would be good to finally get it merged since the syscon bits are a dep for a few other things :) Thanks! Conor. > William Qiu (2): > dt-bindings: soc: starfive: Add StarFive syscon module > riscv: dts: starfive: jh7110: Add syscon nodes > > Xingyu Wu (5): > dt-bindings: clock: Add StarFive JH7110 PLL clock generator > dt-bindings: clock: jh7110-syscrg: Add PLL clock inputs > clk: starfive: Add StarFive JH7110 PLL clock driver > clk: starfive: jh7110-sys: Add PLL clocks source from DTS > riscv: dts: starfive: jh7110: Add PLL clocks source in SYSCRG node > > .../bindings/clock/starfive,jh7110-pll.yaml | 46 ++ > .../clock/starfive,jh7110-syscrg.yaml | 18 +- > .../soc/starfive/starfive,jh7110-syscon.yaml | 93 ++++ > MAINTAINERS | 13 + > arch/riscv/boot/dts/starfive/jh7110.dtsi | 30 +- > drivers/clk/starfive/Kconfig | 9 + > drivers/clk/starfive/Makefile | 1 + > .../clk/starfive/clk-starfive-jh7110-pll.c | 507 ++++++++++++++++++ > .../clk/starfive/clk-starfive-jh7110-sys.c | 45 +- > .../dt-bindings/clock/starfive,jh7110-crg.h | 6 + > 10 files changed, 746 insertions(+), 22 deletions(-) > create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-pll.yaml > create mode 100644 Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml > create mode 100644 drivers/clk/starfive/clk-starfive-jh7110-pll.c > > -- > 2.25.1 >
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