From: Radhey Shyam Pandey <radhey.shyam.pandey@xxxxxxxxxx>
The axiethernet will use dmaengine framework to communicate
with dma controller IP instead of built-in dma programming sequence.
To request dma transmit and receive channels the axiethernet uses
generic dmas, dma-names properties.
Axiethernet may use AXI DMA or MCDMA. DMA has only two channels
where as MCDMA has 16 Tx, 16 Rx channels. To uniquely identify each
channel, we are using 'chan' suffix. Depending on the usecase AXI
ethernet driver can request any combination of multichannel DMA
channels.
Example:
dma-names = tx_chan0, rx_chan0, tx_chan1, rx_chan1;
Also to support the backward compatibility, use "dmas" property to
identify as it should use dmaengine framework or legacy
driver(built-in dma programming).
At this point it is recommended to use dmaengine framework but it's
optional. Once the solution is stable will make dmas as
required properties.
Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xxxxxxxxxx>
Signed-off-by: Sarath Babu Naidu Gaddam <sarath.babu.naidu.gaddam@xxxxxxx>
---
Changes in V4:
1) Updated commit description about tx/rx channels name.
2) Removed "dt-bindings" and "dmaengine" strings in subject.
3) Extended dmas and dma-names to support MCDMA channel names.
1) Remove "driver" from commit message.
2) Use pattern/regex for dma-names property.
Changes in V3:
1) Reverted reg and interrupts property to support backward compatibility.
2) Moved dmas and dma-names properties from Required properties.
Changes in V2:
- None.
---
.../bindings/net/xlnx,axi-ethernet.yaml | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/Documentation/devicetree/bindings/net/xlnx,axi-ethernet.yaml b/Documentation/devicetree/bindings/net/xlnx,axi-ethernet.yaml
index 1d33d80af11c..ea203504b8d4 100644
--- a/Documentation/devicetree/bindings/net/xlnx,axi-ethernet.yaml
+++ b/Documentation/devicetree/bindings/net/xlnx,axi-ethernet.yaml
@@ -122,6 +122,20 @@ properties:
and "phy-handle" should point to an external PHY if exists.
maxItems: 1
+ dmas:
+ minItems: 2
+ maxItems: 32
+ description: DMA Channel phandle and DMA request line number
+
+ dma-names:
+ items:
+ pattern: "^[tr]x_chan[0-9]|1[0-5]$"
+ description:
+ Should be "tx_chan0", "tx_chan1" ... "tx_chan15" for DMA Tx channel
+ Should be "rx_chan0", "rx_chan1" ... "rx_chan15" for DMA Rx channel
+ minItems: 2
+ maxItems: 32
+
required:
- compatible
- interrupts
@@ -143,6 +157,8 @@ examples:
clocks = <&axi_clk>, <&axi_clk>, <&pl_enet_ref_clk>, <&mgt_clk>;
phy-mode = "mii";
reg = <0x40c00000 0x40000>,<0x50c00000 0x40000>;
+ dmas = <&xilinx_dma 0>, <&xilinx_dma 1>;
+ dma-names = "tx_chan0", "rx_chan0";
xlnx,rxcsum = <0x2>;
xlnx,rxmem = <0x800>;
xlnx,txcsum = <0x2>;
--
2.25.1
