This patchset adds USB and PCIe PHY for the StarFive JH7110 SoC. The patch has been tested on the VisionFive 2 board. This patchset is base on v6.4-rc6 patch 1 is usb phy dt-binding document. patch 2 is Pcie PHY dt-binding document. patch 3 is USB 2.0 PHY driver. patch 4 is PCIe PHY driver. patch 5 is PCIe PHY dts Previous version are merged with USB controller patch. For USB controller patch is accepted. Now remove the USB controller patch. And remove the dependency. previous change can be seen list below. (start from old patch set v3) v3: https://patchwork.kernel.org/project/linux-phy/cover/20230315104411.73614-1-minda.chen@xxxxxxxxxxxxxxxx/ v4: https://patchwork.kernel.org/project/linux-phy/cover/20230406015216.27034-1-minda.chen@xxxxxxxxxxxxxxxx/ v5: https://patchwork.kernel.org/project/linux-phy/cover/20230420110052.3182-1-minda.chen@xxxxxxxxxxxxxxxx/ v6: https://patchwork.kernel.org/project/linux-phy/cover/20230518112750.57924-1-minda.chen@xxxxxxxxxxxxxxxx/ v7: https://patchwork.kernel.org/project/linux-phy/cover/20230619094759.21013-1-minda.chen@xxxxxxxxxxxxxxxx/ changes: v8: (patch 3) remame jh7110_usb2_mode_set to usb2_set_ls_keeplive . make function more accurate. (patch 4) remove depend on USB_PHY and fix compile robot error. v7: (patch3 and patch 4) Add /driver/phy/starfive directory, Makefile and Kconfig. Remove the dependency. (patch 5) add PCIe PHY dts configuration. (USB 2.0 PHY clock reply on other patch, Dont add this first). v6: 1. (patch 3) remove the platform remove function. 2. (patch 4) - add switch to pcie mode function. - remove the redundant init/exit function. v5: 1. (patch 1) set correct model name and commit title. 2. (patch 2) change to '-item' in syscon property. change commit title. v4: 1. (patch 1) split PCIe PHY dt-binding doc to patch 2. 2. (patch 2) PCIe PHY add stg and sys con configuration to dt-binding doc. 3. (patch 3) - split PCIe PHY driver to patch 4. - replace dr_mode to phy mode in jh7110_usb2_phy. 4. (patch 4) - Makefile and Kconfig sorted by alphabet sequence. - Add PCIe PHY stg and syscon PHY connection configuration for USB 3.0. v3: 1. Add patch 1 - 4. Add USB PHY driver and dt-binding doc. USB PHY codes are moved to patch 3 and patch 4. Minda Chen (5): dt-bindings: phy: Add StarFive JH7110 USB PHY dt-bindings: phy: Add StarFive JH7110 PCIe PHY phy: starfive: Add JH7110 USB 2.0 PHY driver phy: starfive: Add JH7110 PCIE 2.0 PHY driver riscv: dts: starfive: Add PCIe PHY dts configuration for JH7110 .../phy/starfive,jh7110-pcie-phy.yaml | 58 +++++ .../bindings/phy/starfive,jh7110-usb-phy.yaml | 50 +++++ MAINTAINERS | 8 + arch/riscv/boot/dts/starfive/jh7110.dtsi | 12 ++ drivers/phy/Kconfig | 1 + drivers/phy/Makefile | 1 + drivers/phy/starfive/Kconfig | 24 +++ drivers/phy/starfive/Makefile | 3 + drivers/phy/starfive/phy-jh7110-pcie.c | 204 ++++++++++++++++++ drivers/phy/starfive/phy-jh7110-usb.c | 152 +++++++++++++ 10 files changed, 513 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/starfive,jh7110-pcie-phy.yaml create mode 100644 Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml create mode 100644 drivers/phy/starfive/Kconfig create mode 100644 drivers/phy/starfive/Makefile create mode 100644 drivers/phy/starfive/phy-jh7110-pcie.c create mode 100644 drivers/phy/starfive/phy-jh7110-usb.c base-commit: 858fd168a95c5b9669aac8db6c14a9aeab446375 -- 2.17.1
