On 28.06.2023 11:28, Imran Shaik wrote:
> Fix the gcc_pcie_0_pipe_clk_src clock handling for QDU1000 and
> QRU1000 SoCs.
>
> Fixes: 1c9efb0bc040 ("clk: qcom: Add QDU1000 and QRU1000 GCC support")
> Co-developed-by: Taniya Das <quic_tdas@xxxxxxxxxxx>
> Signed-off-by: Taniya Das <quic_tdas@xxxxxxxxxxx>
> Signed-off-by: Imran Shaik <quic_imrashai@xxxxxxxxxxx>
> ---You could have explained that clk_regmap_phy_mux_ops doesn't implement
any parent-related ops and switches parents implicitly in .enable/disable
Reviewed-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxx>
Konrad
> Changes since v1:
> - Newly added
>
> drivers/clk/qcom/gcc-qdu1000.c | 23 ++++++-----------------
> 1 file changed, 6 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/clk/qcom/gcc-qdu1000.c b/drivers/clk/qcom/gcc-qdu1000.c
> index 5051769ad90c..c00d26a3e6df 100644
> --- a/drivers/clk/qcom/gcc-qdu1000.c
> +++ b/drivers/clk/qcom/gcc-qdu1000.c
> @@ -1,6 +1,6 @@
> // SPDX-License-Identifier: GPL-2.0-only
> /*
> - * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
> + * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
> */
>
> #include <linux/clk-provider.h>
> @@ -370,16 +370,6 @@ static const struct clk_parent_data gcc_parent_data_6[] = {
> { .index = DT_TCXO_IDX },
> };
>
> -static const struct parent_map gcc_parent_map_7[] = {
> - { P_PCIE_0_PIPE_CLK, 0 },
> - { P_BI_TCXO, 2 },
> -};
> -
> -static const struct clk_parent_data gcc_parent_data_7[] = {
> - { .index = DT_PCIE_0_PIPE_CLK_IDX },
> - { .index = DT_TCXO_IDX },
> -};
> -
> static const struct parent_map gcc_parent_map_8[] = {
> { P_BI_TCXO, 0 },
> { P_GCC_GPLL0_OUT_MAIN, 1 },
> @@ -439,16 +429,15 @@ static struct clk_regmap_mux gcc_pcie_0_phy_aux_clk_src = {
> },
> };
>
> -static struct clk_regmap_mux gcc_pcie_0_pipe_clk_src = {
> +static struct clk_regmap_phy_mux gcc_pcie_0_pipe_clk_src = {
> .reg = 0x9d064,
> - .shift = 0,
> - .width = 2,
> - .parent_map = gcc_parent_map_7,
> .clkr = {
> .hw.init = &(const struct clk_init_data) {
> .name = "gcc_pcie_0_pipe_clk_src",
> - .parent_data = gcc_parent_data_7,
> - .num_parents = ARRAY_SIZE(gcc_parent_data_7),
> + .parent_data = &(const struct clk_parent_data){
> + .index = DT_PCIE_0_PIPE_CLK_IDX,
> + },
> + .num_parents = 1,
> .ops = &clk_regmap_phy_mux_ops,
> },
> },
