Re: [PATCH v4 6/6] soc: qcom: llcc: Add QDU1000 and QRU1000 LLCC support

Komal Bajaj <quic_kbajaj@xxxxxxxxxxx> · Wed, 28 Jun 2023 14:23:48 +0530

On 6/23/2023 7:57 PM, Dmitry Baryshkov wrote:
On Fri, 23 Jun 2023 at 17:19, Komal Bajaj <quic_kbajaj@xxxxxxxxxxx> wrote:
Add LLCC configuration data for QDU1000 and QRU1000 SoCs
and updating macro name for LLCC_DRE to LLCC_ECC as per
the latest specification.
Two commits please.

Okay, will split this into two commits.

Thanks
Komal


Signed-off-by: Komal Bajaj <quic_kbajaj@xxxxxxxxxxx>
---
  drivers/soc/qcom/llcc-qcom.c       | 65 +++++++++++++++++++++++++++++-
  include/linux/soc/qcom/llcc-qcom.h |  2 +-
  2 files changed, 65 insertions(+), 2 deletions(-)

diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c
index 3c29612da1c5..d2826158ae60 100644
--- a/drivers/soc/qcom/llcc-qcom.c
+++ b/drivers/soc/qcom/llcc-qcom.c
@@ -187,7 +187,7 @@ static const struct llcc_slice_config sc8280xp_data[] = {
         { LLCC_MMUHWT,   13, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
         { LLCC_DISP,     16, 6144, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
         { LLCC_AUDHW,    22, 2048, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
-       { LLCC_DRE,      26, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
+       { LLCC_ECC,      26, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
         { LLCC_CVP,      28, 512,  3, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 },
         { LLCC_APTCM,    30, 1024, 3, 1, 0x0,   0x1, 1, 0, 0, 1, 0, 0 },
         { LLCC_WRCACHE,  31, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 },
@@ -358,6 +358,36 @@ static const struct llcc_slice_config sm8550_data[] =  {
         {LLCC_VIDVSP,   28,  256, 4, 1, 0xFFFFFF, 0x0,   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
  };

+static const struct llcc_slice_config qdu1000_data_2ch[] = {
+       {LLCC_MDMHPGRW, 7, 512, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 },
+       {LLCC_MODHW,    9, 256, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 },
+       {LLCC_MDMPNG,  21, 256, 0, 1,   0x3, 0x0, 0, 0, 0, 1, 0, 0, 0 },
+       {LLCC_ECC,     26, 512, 3, 1, 0xFFC, 0x0, 0, 0, 0, 0, 1, 0, 0 },
+       {LLCC_MODPE,   29, 256, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 },
+       {LLCC_APTCM,   30, 256, 3, 1,   0x0, 0xC, 1, 0, 0, 1, 0, 0, 0 },
+       {LLCC_WRCACHE, 31, 128, 1, 1,   0x3, 0x0, 0, 0, 0, 0, 1, 0, 0 },
+};
+
+static const struct llcc_slice_config qdu1000_data_4ch[] = {
+       {LLCC_MDMHPGRW, 7, 1024, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 },
+       {LLCC_MODHW,    9, 512,  1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 },
+       {LLCC_MDMPNG,  21, 512,  0, 1,   0x3, 0x0, 0, 0, 0, 1, 0, 0, 0 },
+       {LLCC_ECC,     26, 1024, 3, 1, 0xFFC, 0x0, 0, 0, 0, 0, 1, 0, 0 },
+       {LLCC_MODPE,   29, 512,  1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 },
+       {LLCC_APTCM,   30, 512,  3, 1,   0x0, 0xC, 1, 0, 0, 1, 0, 0, 0 },
+       {LLCC_WRCACHE, 31, 256,  1, 1,   0x3, 0x0, 0, 0, 0, 0, 1, 0, 0 },
+};
+
+static const struct llcc_slice_config qdu1000_data_8ch[] = {
+       {LLCC_MDMHPGRW, 7, 2048, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 },
+       {LLCC_MODHW,    9, 1024, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 },
+       {LLCC_MDMPNG,  21, 1024, 0, 1,   0x3, 0x0, 0, 0, 0, 1, 0, 0, 0 },
+       {LLCC_ECC,     26, 2048, 3, 1, 0xFFC, 0x0, 0, 0, 0, 0, 1, 0, 0 },
+       {LLCC_MODPE,   29, 1024, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 },
+       {LLCC_APTCM,   30, 1024, 3, 1,   0x0, 0xC, 1, 0, 0, 1, 0, 0, 0 },
+       {LLCC_WRCACHE, 31, 512,  1, 1,   0x3, 0x0, 0, 0, 0, 0, 1, 0, 0 },
+};
+
  static const struct llcc_edac_reg_offset llcc_v1_edac_reg_offset = {
         .trp_ecc_error_status0 = 0x20344,
         .trp_ecc_error_status1 = 0x20348,
@@ -557,6 +587,38 @@ static const struct qcom_llcc_config sm8550_cfg[] = {
         { },
  };

+static const struct qcom_llcc_config qdu1000_cfg[] = {
+       {
+               .sct_data       = qdu1000_data_8ch,
+               .size           = ARRAY_SIZE(qdu1000_data_8ch),
+               .need_llcc_cfg  = true,
+               .reg_offset     = llcc_v2_1_reg_offset,
+               .edac_reg_offset = &llcc_v2_1_edac_reg_offset,
+       },
+       {
+               .sct_data       = qdu1000_data_4ch,
+               .size           = ARRAY_SIZE(qdu1000_data_4ch),
+               .need_llcc_cfg  = true,
+               .reg_offset     = llcc_v2_1_reg_offset,
+               .edac_reg_offset = &llcc_v2_1_edac_reg_offset,
+       },
+       {
+               .sct_data       = qdu1000_data_4ch,
+               .size           = ARRAY_SIZE(qdu1000_data_4ch),
+               .need_llcc_cfg  = true,
+               .reg_offset     = llcc_v2_1_reg_offset,
+               .edac_reg_offset = &llcc_v2_1_edac_reg_offset,
+       },
+       {
+               .sct_data       = qdu1000_data_2ch,
+               .size           = ARRAY_SIZE(qdu1000_data_2ch),
+               .need_llcc_cfg  = true,
+               .reg_offset     = llcc_v2_1_reg_offset,
+               .edac_reg_offset = &llcc_v2_1_edac_reg_offset,
+       },
+       { },
+};
+
  static struct llcc_drv_data *drv_data = (void *) -EPROBE_DEFER;

  /**
@@ -1114,6 +1176,7 @@ static int qcom_llcc_probe(struct platform_device *pdev)
  }

  static const struct of_device_id qcom_llcc_of_match[] = {
+       { .compatible = "qcom,qdu1000-llcc", .data = qdu1000_cfg},
         { .compatible = "qcom,sc7180-llcc", .data = sc7180_cfg },
         { .compatible = "qcom,sc7280-llcc", .data = sc7280_cfg },
         { .compatible = "qcom,sc8180x-llcc", .data = sc8180x_cfg },
diff --git a/include/linux/soc/qcom/llcc-qcom.h b/include/linux/soc/qcom/llcc-qcom.h
index 93417ba1ead4..1a886666bbb6 100644
--- a/include/linux/soc/qcom/llcc-qcom.h
+++ b/include/linux/soc/qcom/llcc-qcom.h
@@ -30,7 +30,7 @@
  #define LLCC_NPU         23
  #define LLCC_WLHW        24
  #define LLCC_PIMEM       25
-#define LLCC_DRE         26
+#define LLCC_ECC         26
  #define LLCC_CVP         28
  #define LLCC_MODPE       29
  #define LLCC_APTCM       30
--
2.40.1









