On Tue, Jun 27, 2023 at 06:31:29AM +0530, Krishna chaitanya chundru wrote:
> Some platforms may not boot if a device driver doesn't
> initialize the interconnect path. Mostly it is handled
> by the bootloader but we have starting to see cases
> where bootloader simply ignores them.
>
> Add the "pcie-mem" interconnect path as a required property
> to the bindings.
>
> Signed-off-by: Krishna chaitanya chundru <quic_krichai@xxxxxxxxxxx>
Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx>
- Mani
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx>
> ---
> Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
> index 8111122..bc32e13 100644
> --- a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
> +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
> @@ -71,6 +71,13 @@ properties:
> description: GPIO used as WAKE# output signal
> maxItems: 1
>
> + interconnects:
> + maxItems: 1
> +
> + interconnect-names:
> + items:
> + - const: pcie-mem
> +
> resets:
> maxItems: 1
>
> @@ -98,6 +105,8 @@ required:
> - interrupts
> - interrupt-names
> - reset-gpios
> + - interconnects
> + - interconnect-names
> - resets
> - reset-names
> - power-domains
> @@ -167,7 +176,9 @@ examples:
> - |
> #include <dt-bindings/clock/qcom,gcc-sdx55.h>
> #include <dt-bindings/gpio/gpio.h>
> + #include <dt-bindings/interconnect/qcom,sdx55.h>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> pcie_ep: pcie-ep@1c00000 {
> compatible = "qcom,sdx55-pcie-ep";
> reg = <0x01c00000 0x3000>,
> @@ -194,6 +205,8 @@ examples:
> interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
> interrupt-names = "global", "doorbell";
> + interconnects = <&system_noc MASTER_PCIE &mc_virt SLAVE_EBI_CH0>;
> + interconnect-names = "pcie-mem";
> reset-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>;
> wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>;
> resets = <&gcc GCC_PCIE_BCR>;
> --
> 2.7.4
>
--
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