On Wed, 07 Jun 2023 21:28:24 +0100, Conor Dooley wrote:
> From: Conor Dooley <conor.dooley@xxxxxxxxxxxxx>
>
> With that out of the way, here are some cleanups for our riscv,isa
> handling.
>
> Here are some bits that were discussed with Drew on the "should we
> allow caps" threads that I have now created patches for:
> - splitting of riscv_of_processor_hartid() into two distinct functions,
> one for use purely during early boot, prior to the establishment of
> the possible-cpus mask & another to fit the other current use-cases
> - that then allows us to then completely skip some validation of the
> hartid in the parser
> - the biggest diff in the series is a rework of the comments in the
> parser, as I have mostly found the existing (sparse) ones to not be
> all that helpful whenever I have to go back and look at it
> - from writing the comments, I found a conditional doing a bit of a
> dance that I found counter-intuitive, so I've had a go at making that
> match what I would expect a little better
> - `i` implies 4 other extensions, so add them as extensions and set
> them for the craic. Sure why not like...
>
> [...]
Applied, thanks!
[1/7] RISC-V: simplify register width check in ISA string parsing
https://git.kernel.org/palmer/c/fed14be476f0
[2/7] RISC-V: split early & late of_node to hartid mapping
https://git.kernel.org/palmer/c/2ac874343749
[3/7] RISC-V: validate riscv,isa at boot, not during ISA string parsing
https://git.kernel.org/palmer/c/069b0d517077
[4/7] RISC-V: rework comments in ISA string parser
https://git.kernel.org/palmer/c/6b913e3da87d
[5/7] RISC-V: remove decrement/increment dance in ISA string parser
https://git.kernel.org/palmer/c/7816ebc1ddd1
[6/7] dt-bindings: riscv: explicitly mention assumption of Zicntr & Zihpm support
https://git.kernel.org/palmer/c/1e5cae98e46d
[7/7] RISC-V: always report presence of extensions formerly part of the base ISA
https://git.kernel.org/palmer/c/07edc32779e3
Best regards,
--
Palmer Dabbelt <palmer@xxxxxxxxxxxx>
