Add additional constraints to the CPUfreq-related regulators, it is
better be safe than sorry there.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx>
---
.../boot/dts/qcom/qcom-apq8064-asus-nexus7-flo.dts | 14 ++++++++++++--
1 file changed, 12 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064-asus-nexus7-flo.dts b/arch/arm/boot/dts/qcom/qcom-apq8064-asus-nexus7-flo.dts
index c57c27cd8a20..9f5d72727356 100644
--- a/arch/arm/boot/dts/qcom/qcom-apq8064-asus-nexus7-flo.dts
+++ b/arch/arm/boot/dts/qcom/qcom-apq8064-asus-nexus7-flo.dts
@@ -218,9 +218,9 @@ s1 {
bias-pull-down;
};
- /* msm otg HSUSB_VDDCX */
+ /* msm otg HSUSB_VDDCX and VDD_DIG */
s3 {
- regulator-min-microvolt = <500000>;
+ regulator-min-microvolt = <950000>;
regulator-max-microvolt = <1150000>;
qcom,switch-mode-frequency = <4800000>;
};
@@ -301,6 +301,12 @@ l23 {
bias-pull-down;
};
+ /* VDD_MEM */
+ l24 {
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1150000>;
+ };
+
/*
* tabla2x-slim-CDC_VDDA_A_1P2V
* tabla2x-slim-VDDD_CDC_D
@@ -329,8 +335,12 @@ lvs6 {
/*
* mipi_dsi.1-dsi1_vddio
* pil_riva-pll_vdd
+ * HFPLL regulator
*/
lvs7 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
bias-pull-down;
};
};
--
2.39.2
