On 6/22/2023 5:57 AM, Konrad Dybcio wrote:
Linux should apparently not be concerned with gcc_gpu_bimc_gfx_src_clk and
gcc_gpu_bimc_gfx_src_clk on MSM8998, as they're preconfigured for us.
Unregister them to prevent issues.
You mention the bimc_gfx clock twice here. One of them has to be a typo.
Also, can you clarify the reasoning? The RCG is controlled by the RPM,
but the branch clock is under the control of Linux.
Signed-off-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxx>
---
drivers/clk/qcom/gcc-msm8998.c | 28 ----------------------------
1 file changed, 28 deletions(-)
diff --git a/drivers/clk/qcom/gcc-msm8998.c b/drivers/clk/qcom/gcc-msm8998.c
index ef410f52f09f..980b5a1b58ae 100644
--- a/drivers/clk/qcom/gcc-msm8998.c
+++ b/drivers/clk/qcom/gcc-msm8998.c
@@ -2136,19 +2136,6 @@ static struct clk_branch gcc_gpu_bimc_gfx_clk = {
},
};
-static struct clk_branch gcc_gpu_bimc_gfx_src_clk = {
- .halt_reg = 0x7100c,
- .halt_check = BRANCH_HALT,
- .clkr = {
- .enable_reg = 0x7100c,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_gpu_bimc_gfx_src_clk",
- .ops = &clk_branch2_ops,
- },
- },
-};
-
static struct clk_branch gcc_gpu_cfg_ahb_clk = {
.halt_reg = 0x71004,
.halt_check = BRANCH_HALT_SKIP,
@@ -2168,19 +2155,6 @@ static struct clk_branch gcc_gpu_cfg_ahb_clk = {
},
};
-static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
- .halt_reg = 0x71018,
- .halt_check = BRANCH_HALT,
- .clkr = {
- .enable_reg = 0x71018,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_gpu_snoc_dvm_gfx_clk",
- .ops = &clk_branch2_ops,
- },
- },
-};
-
static struct clk_branch gcc_hmss_ahb_clk = {
.halt_reg = 0x48000,
.halt_check = BRANCH_HALT_VOTED,
@@ -3032,9 +3006,7 @@ static struct clk_regmap *gcc_msm8998_clocks[] = {
[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
[GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr,
[GCC_GPU_BIMC_GFX_CLK] = &gcc_gpu_bimc_gfx_clk.clkr,
- [GCC_GPU_BIMC_GFX_SRC_CLK] = &gcc_gpu_bimc_gfx_src_clk.clkr,
[GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr,
- [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
[GCC_HMSS_AHB_CLK] = &gcc_hmss_ahb_clk.clkr,
[GCC_HMSS_AT_CLK] = &gcc_hmss_at_clk.clkr,
[GCC_HMSS_RBCPR_CLK] = &gcc_hmss_rbcpr_clk.clkr,
