On Thu, 15 Jun 2023 23:50:14 +0100, Conor Dooley wrote: > From: Conor Dooley <conor.dooley@xxxxxxxxxxxxx> > > To permit validation of RISC-V cpu nodes, "additionalProperties: true" > needs to be swapped for "unevaluatedProperties: false". To facilitate > this in a way that passes dt_binding_check, a reference to the cpu > schema is required. > > Disallow the generic cache-op-block-size property that that drags in, > since the RISC-V CBO extensions do not require a common size, and have > individual properties. > > Signed-off-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx> > --- > Documentation/devicetree/bindings/riscv/cpus.yaml | 6 ++++++ > 1 file changed, 6 insertions(+) > Reviewed-by: Rob Herring <robh@xxxxxxxxxx>
