Add dt-binding documentation for Versal NET platforms. Versal Net is a new AMD/Xilinx SoC. The SoC and its architecture is based on the Versal ACAP device. The Versal Net device includes more security features in the platform management controller (PMC) and increases the number of CPUs in the application processing unit (APU) and the real-time processing unit (RPU). Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@xxxxxxxxxx> Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xxxxxxx> --- For the list of peripherals please check https://github.com/Xilinx/u-boot-xlnx/blob/master/arch/arm/dts/versal-net.dtsi Changes in v4: Add description for for versal net Changes in v3: Add the compatible for versal net the usage will new compatible string followed by old one .../devicetree/bindings/clock/xlnx,versal-clk.yaml | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml b/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml index 229af98b1d30..b90aa064a6d3 100644 --- a/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml +++ b/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml @@ -20,7 +20,12 @@ select: false properties: compatible: - const: xlnx,versal-clk + oneOf: + - const: xlnx,versal-clk + - items: + - enum: + - xlnx,versal-net-clk + - const: xlnx,versal-clk "#clock-cells": const: 1 -- 2.17.1
