On Wed, Dec 3, 2014 at 3:22 PM, Dylan Reid <dgreid@xxxxxxxxxxxx> wrote: > On Wed, Dec 3, 2014 at 3:03 PM, Sonny Rao <sonnyrao@xxxxxxxxxxxx> wrote: >> On Wed, Dec 3, 2014 at 12:03 PM, Mark Brown <broonie@xxxxxxxxxx> wrote: >>> On Wed, Dec 03, 2014 at 11:38:13AM -0800, Sonny Rao wrote: >>>> On Wed, Dec 3, 2014 at 11:20 AM, Mark Brown <broonie@xxxxxxxxxx> wrote: >>> >>>> > I would expect that the clock for the CODEC should be managed by the >>>> > CODEC if at all possible - that seems more logical than having the CPU >>>> > I2S controller request and manage it if it's a separate clock. Why add >>>> > this to the CPU side driver? >>> >>>> This output clock has a mux and can either be a fixed 12Mhz output or >>>> can be derived from the same fractional divider which drives the i2s >>>> block. I thought it was simpler to keep them all the same, but need >>>> to put ownership in the i2s in anticipation of the i2s driver setting >>>> it's own clock rate. >>> >>>> If you think this is an implementation detail and this output clock >>>> should just be owned by the codec driver, even though I'm guessing it >>>> will just have to be the same as i2s, then I think we can drop this >>>> and make sure simple card (or whatever other codec driver) claims this >>>> clock. >>> >>> simple-card obviously isn't a CODEC driver... >> >> Yeah, sorry. >> >>> For generality I think >>> the clock does need to be exposed to the CODEC driver, otherwise this >>> will work differently to how other systems are working and we can't >>> substitute in a different clock on the CODEC side so easily if it >>> doesn't happen to use the output from the I2S block. >> >> Ok, then I think what we will do is abandon this patch and I will send >> something that adds this functionality to the particular codec that >> I'm interested in -- max98090. > > Sorry I didn't read this earlier. I don't think that this belongs in > the max98090. The original patch description is a bit confusing. The > clock being grabbed here is actually i2s mclk. My understanding is > that, on this SoC, the mclk is driven from a different IP block than > the rest of the i2s signals. The i2s driver needs to be told about > the clock and enable/disable it at the appropriate times. I'm > assuming it's optional because there are boards using this SoC with > i2s slave mode that don't drive mclk at all. > > Please correct me if I'm wrong on any of the above. I don't think you're wrong, and I'm an audio/i2s neophyte so I think you're probably right and hopefully Mark can confirm that this is how we want it. One important thing to point out, which might be causing confusion, is that this driver is claiming a clock which it internally calls "mclk" but the way it's specified for rk3288 in the DT, that one is just the one which drives the internal logic and has a gate. This clock I'm adding is the actual mclk which is being driven to the i2s slave device, and it has it's own gate and also has a mux, and we need to claim both to be able to enable proper clock gating. -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
