Allow a single HS port to be used e.g. without reg property and a unit
address. OF graph allows a single port node, without 'reg' property.
This removes a couple of Warnings or errors on STM32MP boards.
When using single HS port currently, when doing building with W=1:
arch/arm/boot/dts/stm32mp157c-dk2.dtb: stusb1600@28: connector:
Unevaluated properties are not allowed ('port' was unexpected)
Signed-off-by: Fabrice Gasnier <fabrice.gasnier@xxxxxxxxxxx>
---
Notes: Other attempts seem to lead to a dead end. Ex: by updating the
relevant dts files, to use ports, and port@0, make W=1 shows
...connector/ports: graph node has single child node
'port@0', #address-cells/#size-cells are not necessary.
But not adding them lead to another "Warning (avoid_default_addr_size)"
---
.../bindings/connector/usb-connector.yaml | 20 +++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/Documentation/devicetree/bindings/connector/usb-connector.yaml b/Documentation/devicetree/bindings/connector/usb-connector.yaml
index ae515651fc6b..1c4d3eb87763 100644
--- a/Documentation/devicetree/bindings/connector/usb-connector.yaml
+++ b/Documentation/devicetree/bindings/connector/usb-connector.yaml
@@ -168,6 +168,13 @@ properties:
offer the power, Capability Mismatch is set. Required for power sink and
power dual role.
+ port:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: OF graph bindings modeling a data bus to the connector, e.g.
+ there is a single High Speed (HS) port present in this connector. If there
+ is more than one bus (several port, with 'reg' property), they can be grouped
+ under 'ports'.
+
ports:
$ref: /schemas/graph.yaml#/properties/ports
description: OF graph bindings modeling any data bus to the connector
@@ -322,6 +329,19 @@ examples:
};
};
+ # USB-C connector attached to SoC with a single High-Speed controller
+ - |
+ connector {
+ compatible = "usb-c-connector";
+ label = "USB-C";
+
+ port {
+ high_speed_ep: endpoint {
+ remote-endpoint = <&usb_hs_ep>;
+ };
+ };
+ };
+
# USB-C connector attached to SoC and USB3 typec port controller(hd3ss3220)
# with SS 2:1 MUX. HS lines routed to SoC, SS lines routed to the MUX and
# the output of MUX is connected to the SoC.
--
2.25.1
