On 17.06.2023 22:41, Krzysztof Kozlowski wrote:
> Qualcomm Operating State Manager (OSM) L3 Interconnect does not take
> path (third) argument. This was introduced by commit 97c289026c62
> ("arm64: dts: qcom: sm8150: Use 2 interconnect cells") which probably
> wanted to use 2 cells only for RPMh interconnects.
>
> sm8150-microsoft-surface-duo.dtb: interconnect@18321000: #interconnect-cells:0:0: 1 was expected
>
> Fixes: 97c289026c62 ("arm64: dts: qcom: sm8150: Use 2 interconnect cells")
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx>
> ---
Ouch that's an oversight
Reviewed-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxx>
On a note, the L3 interconnect has per-CPU (or realistically, per-cluster)
voting buckets, but we don't use them as it just seems like an
overcomplication with no immediately obvious benefits.
Konrad
> arch/arm64/boot/dts/qcom/sm8150.dtsi | 18 +++++++++---------
> 1 file changed, 9 insertions(+), 9 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
> index 18c822abdb88..b46e55bb8bde 100644
> --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
> @@ -56,7 +56,7 @@ CPU0: cpu@0 {
> qcom,freq-domain = <&cpufreq_hw 0>;
> operating-points-v2 = <&cpu0_opp_table>;
> interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
> - <&osm_l3 MASTER_OSM_L3_APPS 0 &osm_l3 SLAVE_OSM_L3 0>;
> + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
> power-domains = <&CPU_PD0>;
> power-domain-names = "psci";
> #cooling-cells = <2>;
> @@ -85,7 +85,7 @@ CPU1: cpu@100 {
> qcom,freq-domain = <&cpufreq_hw 0>;
> operating-points-v2 = <&cpu0_opp_table>;
> interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
> - <&osm_l3 MASTER_OSM_L3_APPS 0 &osm_l3 SLAVE_OSM_L3 0>;
> + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
> power-domains = <&CPU_PD1>;
> power-domain-names = "psci";
> #cooling-cells = <2>;
> @@ -109,7 +109,7 @@ CPU2: cpu@200 {
> qcom,freq-domain = <&cpufreq_hw 0>;
> operating-points-v2 = <&cpu0_opp_table>;
> interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
> - <&osm_l3 MASTER_OSM_L3_APPS 0 &osm_l3 SLAVE_OSM_L3 0>;
> + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
> power-domains = <&CPU_PD2>;
> power-domain-names = "psci";
> #cooling-cells = <2>;
> @@ -133,7 +133,7 @@ CPU3: cpu@300 {
> qcom,freq-domain = <&cpufreq_hw 0>;
> operating-points-v2 = <&cpu0_opp_table>;
> interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
> - <&osm_l3 MASTER_OSM_L3_APPS 0 &osm_l3 SLAVE_OSM_L3 0>;
> + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
> power-domains = <&CPU_PD3>;
> power-domain-names = "psci";
> #cooling-cells = <2>;
> @@ -157,7 +157,7 @@ CPU4: cpu@400 {
> qcom,freq-domain = <&cpufreq_hw 1>;
> operating-points-v2 = <&cpu4_opp_table>;
> interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
> - <&osm_l3 MASTER_OSM_L3_APPS 0 &osm_l3 SLAVE_OSM_L3 0>;
> + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
> power-domains = <&CPU_PD4>;
> power-domain-names = "psci";
> #cooling-cells = <2>;
> @@ -181,7 +181,7 @@ CPU5: cpu@500 {
> qcom,freq-domain = <&cpufreq_hw 1>;
> operating-points-v2 = <&cpu4_opp_table>;
> interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
> - <&osm_l3 MASTER_OSM_L3_APPS 0 &osm_l3 SLAVE_OSM_L3 0>;
> + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
> power-domains = <&CPU_PD5>;
> power-domain-names = "psci";
> #cooling-cells = <2>;
> @@ -205,7 +205,7 @@ CPU6: cpu@600 {
> qcom,freq-domain = <&cpufreq_hw 1>;
> operating-points-v2 = <&cpu4_opp_table>;
> interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
> - <&osm_l3 MASTER_OSM_L3_APPS 0 &osm_l3 SLAVE_OSM_L3 0>;
> + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
> power-domains = <&CPU_PD6>;
> power-domain-names = "psci";
> #cooling-cells = <2>;
> @@ -229,7 +229,7 @@ CPU7: cpu@700 {
> qcom,freq-domain = <&cpufreq_hw 2>;
> operating-points-v2 = <&cpu7_opp_table>;
> interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
> - <&osm_l3 MASTER_OSM_L3_APPS 0 &osm_l3 SLAVE_OSM_L3 0>;
> + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
> power-domains = <&CPU_PD7>;
> power-domain-names = "psci";
> #cooling-cells = <2>;
> @@ -4342,7 +4342,7 @@ osm_l3: interconnect@18321000 {
> clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
> clock-names = "xo", "alternate";
>
> - #interconnect-cells = <2>;
> + #interconnect-cells = <1>;
> };
>
> cpufreq_hw: cpufreq@18323000 {
