On Wed, Jun 14, 2023 at 09:47:53PM +0530, Anup Patel wrote: > On Wed, Jun 14, 2023 at 8:16 PM Jason Gunthorpe <jgg@xxxxxxxx> wrote: > > > > On Tue, Jun 13, 2023 at 09:04:11PM +0530, Anup Patel wrote: > > > We have a separate RISC-V IMSIC MSI address for each CPU so changing > > > MSI (or IRQ) affinity results in re-programming of MSI address in > > > the PCIe (or platform) device. > > > > > > Currently, the iommu_dma_prepare_msi() is called only once at the > > > time of IRQ allocation so IOMMU DMA domain will only have mapping > > > for one MSI page. This means iommu_dma_compose_msi_msg() called > > > by imsic_irq_compose_msi_msg() will always use the same MSI page > > > irrespective to target CPU MSI address. In other words, changing > > > MSI (or IRQ) affinity for device using IOMMU DMA domain will not > > > work. > > > > You didn't answer my question from last time - there seems to be no > > iommu driver here so why are you messing with iommu_dma_prepare_msi()? > > > > This path is only for platforms that have IOMMU drivers that translate > > the MSI window. You should add this code to link the interrupt > > controller to the iommu driver when you introduce the iommu driver, > > not in this series? > > > > And, as I said before, I'd like to NOT see new users of > > iommu_dma_prepare_msi() since it is a very problematic API. > > > > This hacking of it here is not making it better :( > > I misunderstood your previous comments. > > We can certainly deal with this later when the IOMMU > driver is available for RISC-V. I will drop this patch in the > next revision. Not only just this patch but the calls to iommu_dma_prepare_msi() and related APIs in the prior patch too. Assume the MSI window is directly visible to DMA without translation. When you come with an iommu driver we can discuss how best to proceed. Thanks, Jason
