On 13/06/2023 14:58, Xingyu Wu wrote: > Add optional PLL clock inputs from PLL clock generator. Are you sure that PLLs are optional? Usually they are not... > > Signed-off-by: Xingyu Wu <xingyu.wu@xxxxxxxxxxxxxxxx> > --- > .../clock/starfive,jh7110-syscrg.yaml | 56 +++++++++++++++++++ > 1 file changed, 56 insertions(+) > > diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml > index 84373ae31644..5536e5f9e20b 100644 > --- a/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml > +++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml > @@ -39,6 +39,33 @@ properties: > - description: External TDM clock > - description: External audio master clock > > + - items: > + - description: Main Oscillator (24 MHz) > + - description: GMAC1 RMII reference or GMAC1 RGMII RX > + - description: External I2S TX bit clock > + - description: External I2S TX left/right channel clock > + - description: External I2S RX bit clock > + - description: External I2S RX left/right channel clock > + - description: External TDM clock > + - description: External audio master clock > + - description: PLL0 > + - description: PLL1 > + - description: PLL2 Add these three to the existing entry with minItems. > + > + - items: > + - description: Main Oscillator (24 MHz) > + - description: GMAC1 RMII reference > + - description: GMAC1 RGMII RX > + - description: External I2S TX bit clock > + - description: External I2S TX left/right channel clock > + - description: External I2S RX bit clock > + - description: External I2S RX left/right channel clock > + - description: External TDM clock > + - description: External audio master clock > + - description: PLL0 > + - description: PLL1 > + - description: PLL2 Add these three to the existing entry with minItems. > + > clock-names: > oneOf: > - items: > @@ -64,6 +91,35 @@ properties: > - const: tdm_ext > - const: mclk_ext > > + - items: > + - const: osc > + - enum: > + - gmac1_rmii_refin > + - gmac1_rgmii_rxin > + - const: i2stx_bclk_ext > + - const: i2stx_lrck_ext > + - const: i2srx_bclk_ext > + - const: i2srx_lrck_ext > + - const: tdm_ext > + - const: mclk_ext > + - const: pll0_out > + - const: pll1_out > + - const: pll2_out Add these three to the existing entry with minItems. > + > + - items: > + - const: osc > + - const: gmac1_rmii_refin > + - const: gmac1_rgmii_rxin > + - const: i2stx_bclk_ext > + - const: i2stx_lrck_ext > + - const: i2srx_bclk_ext > + - const: i2srx_lrck_ext > + - const: tdm_ext > + - const: mclk_ext > + - const: pll0_out > + - const: pll1_out > + - const: pll2_out Add these three to the existing entry with minItems. Best regards, Krzysztof
