Hi, This enables SATA support for RK3588. Changes since PATCHv3: * https://lore.kernel.org/all/20230608162238.50078-1-sebastian.reichel@xxxxxxxxxxxxx/ * Add Reviewed-by from Serge and Krzysztof to patch 1 * Update patch 2 - Add maxItems to 'clocks' property; without specifying minItems it's implied to be the same - Keep allOf above the properties in snps,dwc-ahci.yaml - Add 'sata-port@0' to list of allowed properties - Replace sata-port pattern property, so that it disallows using any sata-port nodes besides @0 to override the pattern property from the common binding * Add Reviewed-by from Krzysztof to patch 3 Changes since PATCHv2: * https://lore.kernel.org/all/20230522173423.64691-1-sebastian.reichel@xxxxxxxxxxxxx/ * Drop patch 1 (applied by Heiko) * Update SATA DT binding to split Rockchip into its own file * Enforce correct resets numbers for the rk3568/rk3588 combo PHY Changes since PATCHv1: * https://lore.kernel.org/all/20230413182345.92557-1-sebastian.reichel@xxxxxxxxxxxxx/ * Rebase to v6.4-rc1 * Collect Acked-by for syscon DT binding update * Use ASIC clock description suggested by Serge Semin * Also add RBC clock (not used by RK3588) * Add extra patch narrowing down the allowed clocks for RK356x and RK3588 -- Sebastian Sebastian Reichel (5): dt-bindings: ata: dwc-ahci: add PHY clocks dt-bindings: ata: dwc-ahci: add Rockchip RK3588 dt-bindings: phy: rockchip: rk3588 has two reset lines arm64: dts: rockchip: rk3588: add combo PHYs arm64: dts: rockchip: rk3588: add SATA support .../bindings/ata/rockchip,dwc-ahci.yaml | 124 ++++++++++++++++++ .../bindings/ata/snps,dwc-ahci-common.yaml | 8 +- .../bindings/ata/snps,dwc-ahci.yaml | 13 +- .../phy/phy-rockchip-naneng-combphy.yaml | 34 ++++- arch/arm64/boot/dts/rockchip/rk3588.dtsi | 44 +++++++ arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 90 +++++++++++++ 6 files changed, 306 insertions(+), 7 deletions(-) create mode 100644 Documentation/devicetree/bindings/ata/rockchip,dwc-ahci.yaml -- 2.39.2
