The DP output is shared with the USB3 SuperSpeed lanes and is usually connected to an USB-C port which Altmode is controlled by the PMIC Glink infrastructure. DT changes tying the DP controller to the USB-C port on the QRD board will be sent later. Signed-off-by: Neil Armstrong <neil.armstrong@xxxxxxxxxx> --- Changes in v3: - Rebased on next-20230609 - Dropped applied bindings - Link to v2: https://lore.kernel.org/r/20230601-topic-sm8550-upstream-dp-v2-0-e8778109c757@xxxxxxxxxx Changes in v2: - Added review tags - s/lov_svs/low_svs/ - Applied fixes suggested from Konrad - Link to v1: https://lore.kernel.org/r/20230601-topic-sm8550-upstream-dp-v1-0-29efe2689553@xxxxxxxxxx --- Neil Armstrong (2): arm64: dts: qcom: sm8550: fix low_svs RPMhPD labels arm64: dts: qcom: sm8550: add display port nodes arch/arm64/boot/dts/qcom/sm8550.dtsi | 95 ++++++++++++++++++++++++++++++++++-- 1 file changed, 90 insertions(+), 5 deletions(-) --- base-commit: 53ab6975c12d1ad86c599a8927e8c698b144d669 change-id: 20230601-topic-sm8550-upstream-dp-b713ba275d7c Best regards, -- Neil Armstrong <neil.armstrong@xxxxxxxxxx>
