From: Conor Dooley <conor.dooley@xxxxxxxxxxxxx> To allow setting "unevaluatedProperties: false" for cpus.yaml, permit the operating points property for RISC-V cpu nodes. Signed-off-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx> --- Documentation/devicetree/bindings/riscv/cpus.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index 9bf2b72a9460..00d1e273f1a9 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -108,6 +108,7 @@ properties: # RISC-V has multiple properties for cache op block sizes as the sizes # differ between individual CBO extensions cache-op-block-size: false + operating-points-v2: true # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here timebase-frequency: false -- 2.39.2
