On 6/7/2023 5:43 PM, Krzysztof Kozlowski wrote:
On 07/06/2023 13:47, Rohit Agarwal wrote:Add basic devicetree support for SDX75 platform and IDP board from Qualcomm. The SDX75 platform features an ARM Cortex A55 CPU which forms the Application Processor Sub System (APSS) along with standard Qualcomm peripherals like GCC, TLMM, UART, QPIC, and BAM etc... Also, there exists the networking parts such as IPA, MHI, PCIE-EP, EMAC, and Modem etc.. Signed-off-by: Rohit Agarwal <quic_rohiagar@xxxxxxxxxxx> --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/sdx75-idp.dts | 33 ++ arch/arm64/boot/dts/qcom/sdx75.dtsi | 660 +++++++++++++++++++++++++++++++++ 3 files changed, 694 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sdx75-idp.dts create mode 100644 arch/arm64/boot/dts/qcom/sdx75.dtsi diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index d42c595..4fd5a18 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -173,6 +173,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm845-xiaomi-polaris.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-shift-axolotl.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm850-lenovo-yoga-c630.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm850-samsung-w737.dtb +dtb-$(CONFIG_ARCH_QCOM) += sdx75-idp.dtb dtb-$(CONFIG_ARCH_QCOM) += sm4250-oneplus-billie2.dtb dtb-$(CONFIG_ARCH_QCOM) += sm6115p-lenovo-j606f.dtb dtb-$(CONFIG_ARCH_QCOM) += sm6125-sony-xperia-seine-pdx201.dtb diff --git a/arch/arm64/boot/dts/qcom/sdx75-idp.dts b/arch/arm64/boot/dts/qcom/sdx75-idp.dts new file mode 100644 index 0000000..cbe5cdf --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sdx75-idp.dts @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "sdx75.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDX75 IDP"; + compatible = "qcom,sdx75-idp", "qcom,sdx75"; + + aliases { + serial0 = &uart1; + }; +}; + +&chosen { + stdout-path = "serial0:115200n8"; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&tlmm { + gpio-reserved-ranges = <110 6>; +}; + +&uart1 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/sdx75.dtsi b/arch/arm64/boot/dts/qcom/sdx75.dtsi new file mode 100644 index 0000000..40fa579 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sdx75.dtsi @@ -0,0 +1,660 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * SDX75 SoC device tree source + * + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + */ + +#include <dt-bindings/clock/qcom,rpmh.h> +#include <dt-bindings/clock/qcom,sdx75-gcc.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/soc/qcom,rpmh-rsc.h> + +/ { + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&intc>; + + chosen: chosen { }; + + clocks { + xo_board: xo-board { + compatible = "fixed-clock"; + clock-frequency = <76800000>; + #clock-cells = <0>; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + clock-frequency = <32000>; + #clock-cells = <0>; + }; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x0>; + clocks = <&cpufreq_hw 0>; + enable-method = "psci"; + power-domains = <&CPU_PD0>; + power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 0>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + next-level-cache = <&L2_0>; + + L2_0: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>;You miss properties like level and unified. Maybye you tested it with some old (half year ago) dtschema? It does not look like you tested the DTS against bindings. Please run `make dtbs_check` (see Documentation/devicetree/bindings/writing-schema.rst for instructions).
Let me check the latest bindings and update. Thanks, Rohit.
Best regards, Krzysztof
