There are certain SMMUs on qcom SoCs, which need to set interconnect- bandwidth, before accessing any MIMO mapped HW registers, and accessing RAM during page table walk. Hence introduce the due bindings for interconnects. Reported-by: Eric Chanudet <echanude@xxxxxxxxxx> Signed-off-by: Parikshit Pareek <quic_ppareek@xxxxxxxxxxx> --- .../devicetree/bindings/iommu/arm,smmu.yaml | 22 +++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml index ba677d401e24..75e00789d8c2 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml @@ -327,6 +327,28 @@ allOf: - description: interface clock required to access smmu's registers through the TCU's programming interface. + - if: + properties: + compatible: + contains: + enum: + qcom,sa8775p-smmu-500 + then: + properties: + interconnects: + minItems: 1 + maxItems: 1 + + interconnect-names: + minItems: 1 + items: + - const: tbu_mc + + icc_bw: + $ref: /schemas/types.yaml#/definitions/int32 + description: + An integer expressing the interconnect bandwidth(MBps) to be set. + - if: properties: compatible: -- 2.17.1