On Mon, May 29, 2023 at 04:30:58PM +0200, Guillaume Ranquet wrote: > Add mt8195 SoC bindings for hdmi and hdmi-ddc > > On mt8195 the ddc i2c controller is part of the hdmi IP block and thus has no > specific register range, power domain or interrupt, making it simpler > than the legacy "mediatek,hdmi-ddc" binding. > > Signed-off-by: Guillaume Ranquet <granquet@xxxxxxxxxxxx> > --- > .../bindings/display/mediatek/mediatek,hdmi.yaml | 59 ++++++++++++++++++---- > .../display/mediatek/mediatek,mt8195-hdmi-ddc.yaml | 45 +++++++++++++++++ > 2 files changed, 93 insertions(+), 11 deletions(-) > > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.yaml > index b90b6d18a828..4f62e6b94048 100644 > --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.yaml > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.yaml > @@ -21,6 +21,7 @@ properties: > - mediatek,mt7623-hdmi > - mediatek,mt8167-hdmi > - mediatek,mt8173-hdmi > + - mediatek,mt8195-hdmi > > reg: > maxItems: 1 > @@ -29,18 +30,10 @@ properties: > maxItems: 1 > > clocks: > - items: > - - description: Pixel Clock > - - description: HDMI PLL > - - description: Bit Clock > - - description: S/PDIF Clock > + maxItems: 4 > > clock-names: > - items: > - - const: pixel > - - const: pll > - - const: bclk > - - const: spdif > + maxItems: 4 > > phys: > maxItems: 1 > @@ -58,6 +51,9 @@ properties: > description: | > phandle link and register offset to the system configuration registers. > > + power-domains: > + maxItems: 1 > + > ports: > $ref: /schemas/graph.yaml#/properties/ports > > @@ -86,9 +82,50 @@ required: > - clock-names > - phys > - phy-names > - - mediatek,syscon-hdmi > - ports > > +allOf: > + - if: > + properties: > + compatible: > + contains: > + const: mediatek,mt8195-hdmi > + then: > + properties: > + clocks: > + items: > + - description: APB > + - description: HDCP > + - description: HDCP 24M > + - description: Split HDMI > + clock-names: > + items: > + - const: hdmi_apb_sel > + - const: hdcp_sel > + - const: hdcp24_sel > + - const: split_hdmi > + > + required: > + - power-domains > + else: > + properties: > + clocks: > + items: > + - description: Pixel Clock > + - description: HDMI PLL > + - description: Bit Clock > + - description: S/PDIF Clock > + > + clock-names: > + items: > + - const: pixel > + - const: pll > + - const: bclk > + - const: spdif I don't understand how the same h/w block can have completely different clocks. If not the same h/w or evolution of the same h/w, then do a separate schema. > + > + required: > + - mediatek,syscon-hdmi > + > additionalProperties: false > > examples: > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml > new file mode 100644 > index 000000000000..84c096835b47 > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml > @@ -0,0 +1,45 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Mediatek HDMI DDC for mt8195 > + > +maintainers: > + - CK Hu <ck.hu@xxxxxxxxxxxx> > + - Jitao shi <jitao.shi@xxxxxxxxxxxx> > + > +description: | > + The HDMI DDC i2c controller is used to interface with the HDMI DDC pins. > + > +properties: > + compatible: > + enum: > + - mediatek,mt8195-hdmi-ddc > + > + clocks: > + maxItems: 1 > + > + mediatek,hdmi: > + $ref: /schemas/types.yaml#/definitions/phandle > + description: > + A phandle to the mt8195 hdmi controller > + > +required: > + - compatible > + - clocks > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + #include <dt-bindings/interrupt-controller/irq.h> > + hdmiddc0: i2c { > + compatible = "mediatek,mt8195-hdmi-ddc"; > + mediatek,hdmi = <&hdmi0>; > + clocks = <&clk26m>; How does one access this h/w device? There is nothing described to access it. Rob
