On 05/06/2023 11:52, Tony Lindgren wrote: > Update binding for yaml and remove the old related txt bindings. Note that > we are also adding the undocumented pinctrl-single,slew-rate property. And > we only use the first example from the old binding. > > Cc: Nishanth Menon <nm@xxxxxx> > Cc: Vignesh Raghavendra <vigneshr@xxxxxx> > Signed-off-by: Tony Lindgren <tony@xxxxxxxxxxx> > --- > > Changes since v5: > - Fix issues noted by Krzysztof > diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-single.yaml b/Documentation/devicetree/bindings/pinctrl/pinctrl-single.yaml > new file mode 100644 > --- /dev/null > +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-single.yaml > @@ -0,0 +1,206 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/pinctrl/pinctrl-single.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Pinctrl driver for hardware with a single register for one or more pins I asked to drop the driver references but it is still here. Bindings are not describing drivers. "Generic Pin Controller with a Single Register for One or More Pins" > + > +maintainers: > + - Tony Lindgren <tony@xxxxxxxxxxx> > + > +description: > + Some pin controller devices use a single register for one or more pins. The > + range of pin control registers can vary from one to many for each controller > + instance. Some SoCs from Altera, Broadcom, HiSilicon, Ralink, and TI have this > + kind of pin controller instances. > + > +properties: > + compatible: > + oneOf: > + - enum: > + - pinctrl-single > + - pinconf-single > + - items: > + - enum: > + - ti,am437-padconf > + - ti,dra7-padconf > + - ti,omap2420-padconf > + - ti,omap2430-padconf > + - ti,omap3-padconf > + - ti,omap4-padconf > + - ti,omap5-padconf > + - const: pinctrl-single > + > + reg: > + maxItems: 1 > + > + interrupt-controller: true > + > + '#interrupt-cells': > + const: 1 > + > + '#address-cells': > + const: 1 > + > + '#size-cells': > + const: 0 > + > + '#pinctrl-cells': > + description: > + Number of cells. Usually 2, consisting of register offset, pin configuration > + value, and pinmux mode. Some controllers may use 1 for just offset and value. > + enum: [ 1, 2 ] > + > + pinctrl-single,bit-per-mux: > + description: Optional flag to indicate register controls more than one pin > + type: boolean > + > + pinctrl-single,function-mask: > + description: Mask of the allowed register bits > + $ref: /schemas/types.yaml#/definitions/uint32 > + > + pinctrl-single,function-off: > + description: Optional function off mode for disabled state > + $ref: /schemas/types.yaml#/definitions/uint32 > + > + pinctrl-single,register-width: > + description: Width of pin specific bits in the register > + $ref: /schemas/types.yaml#/definitions/uint32 > + enum: [ 8, 16, 32 ] > + > + pinctrl-single,gpio-range: > + description: Optional list of pin base, nr pins & gpio function > + $ref: /schemas/types.yaml#/definitions/phandle-array > + items: > + - items: > + - description: phandle of a gpio-range node > + - description: pin base > + - description: number of pins > + - description: gpio function > + > + '#gpio-range-cells': > + description: No longer needed, may exist in older files for gpio-ranges > + deprecated: true > + const: 3 > + > + gpio-range: > + description: Optional node for gpio range cells > + type: object > + additionalProperties: false > + properties: > + '#pinctrl-single,gpio-range-cells': > + description: Number of gpio range cells > + const: 3 > + $ref: /schemas/types.yaml#/definitions/uint32 > + > +patternProperties: > + '-pins$|-pin': you did not implement my comments fully, probably we misunderstood each other. Why do you allow anything after '-pin'? Let's make it pure suffix for both cases: '-pins?$' > + description: > + Pin group node name using naming ending in -pins, or having -pin > + in the node name > + type: object > + additionalProperties: false > + Best regards, Krzysztof
