On Wed, May 10, 2023 at 03:22:24PM +0900, Yoshihiro Shimoda wrote:
> dw_pcie_setup() will set PCI_EXP_LNKSTA_NLW to PCI_EXP_LNKCAP register
> so that drop such setting from tegra_pcie_dw_host_init().
>
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@xxxxxxxxxxx>
> Cc: Thierry Reding <thierry.reding@xxxxxxxxx>
> Cc: Jonathan Hunter <jonathanh@xxxxxxxxxx>
AFAICS this update isn't supposed to bring any regression since the
tegra_pcie_dw_host_init() call is always followed by the
dw_pcie_setup_rc() method invocation which thanks to your patches now
fully performs the link width setups. So from my point of view:
Reviewed-by: Serge Semin <fancer.lancer@xxxxxxxxx>
Though testing this on a real hw would be very welcome.
-Serge(y)
> ---
> drivers/pci/controller/dwc/pcie-tegra194.c | 6 ------
> 1 file changed, 6 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
> index 4adba379b83d..723a22ccd58c 100644
> --- a/drivers/pci/controller/dwc/pcie-tegra194.c
> +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
> @@ -901,12 +901,6 @@ static int tegra_pcie_dw_host_init(struct dw_pcie_rp *pp)
> AMBA_ERROR_RESPONSE_CRS_SHIFT);
> dw_pcie_writel_dbi(pci, PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT, val);
>
> - /* Configure Max lane width from DT */
> - val = dw_pcie_readl_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKCAP);
> - val &= ~PCI_EXP_LNKCAP_MLW;
> - val |= (pcie->num_lanes << PCI_EXP_LNKSTA_NLW_SHIFT);
> - dw_pcie_writel_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKCAP, val);
> -
> /* Clear Slot Clock Configuration bit if SRNS configuration */
> if (pcie->enable_srns) {
> val_16 = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base +
> --
> 2.25.1
>
