Re: [PATCH V3 2/5] clk: qcom: Remove support to set CAL_L field in lucid evo pll configure

[Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx>]

On 01/06/2023 17:34, Jagadeesh Kona wrote:
> For lucid evo and ole pll's the CAL_L, RINGOSC_CAL_L and L_VAL are
> part of the same register, hence update the l configuration value
> to include these fields across all the chipsets.
>
> Since the l configuration value now includes both L and CAL_L fields,
> there is no need to explicitly set CAL_L field again in lucid evo pll
> configure, Hence remove support to explicity set CAL_L field for evo pll.
>
> Fixes: 260e36606a03 ("clk: qcom: clk-alpha-pll: add Lucid EVO PLL configuration interfaces")
> Signed-off-by: Taniya Das <quic_tdas@xxxxxxxxxxx>
> Signed-off-by: Jagadeesh Kona <quic_jkona@xxxxxxxxxxx>
> ---
> Changes since V2:
>   - Squashed update L val and remove explicit cal_l configuration to single patch
>   - Updated L configuration for gpucc-sm8450 as well which was merged recently
> Changes since V1:
>   - Newly added.
>
>   drivers/clk/qcom/camcc-sm8450.c  | 24 ++++++++++++++++--------
>   drivers/clk/qcom/clk-alpha-pll.c |  6 +-----
>   drivers/clk/qcom/dispcc-sm8450.c |  6 ++++--
>   drivers/clk/qcom/dispcc-sm8550.c |  6 ++++--
>   drivers/clk/qcom/gpucc-sa8775p.c |  6 ++++--
>   drivers/clk/qcom/gpucc-sm8450.c  |  6 ++++--
>   6 files changed, 33 insertions(+), 21 deletions(-)

I'd say, this is still not a correct solution from my point of view. A 
correct solution would be to follow the existing code and use constants 
for the constant values (of CAL_L, and RINGOSC_CAL_L).

> diff --git a/drivers/clk/qcom/camcc-sm8450.c b/drivers/clk/qcom/camcc-sm8450.c
> index 51338a2884d2..6a5a08f88598 100644
> --- a/drivers/clk/qcom/camcc-sm8450.c
> +++ b/drivers/clk/qcom/camcc-sm8450.c
> @@ -57,7 +57,8 @@ static const struct pll_vco rivian_evo_vco[] = {
>   static const struct clk_parent_data pll_parent_data_tcxo = { .index = DT_BI_TCXO };
>   
>   static const struct alpha_pll_config cam_cc_pll0_config = {
> -	.l = 0x3e,
> +	/* .l includes CAL_L_VAL, L_VAL fields */
> +	.l = 0x0044003e,
>   	.alpha = 0x8000,
>   	.config_ctl_val = 0x20485699,
>   	.config_ctl_hi_val = 0x00182261,
> @@ -128,7 +129,8 @@ static struct clk_alpha_pll_postdiv cam_cc_pll0_out_odd = {
>   };
>   
>   static const struct alpha_pll_config cam_cc_pll1_config = {
> -	.l = 0x25,
> +	/* .l includes CAL_L_VAL, L_VAL fields */
> +	.l = 0x00440025,
>   	.alpha = 0xeaaa,
>   	.config_ctl_val = 0x20485699,
>   	.config_ctl_hi_val = 0x00182261,
> @@ -199,7 +201,8 @@ static struct clk_alpha_pll cam_cc_pll2 = {
>   };
>   
>   static const struct alpha_pll_config cam_cc_pll3_config = {
> -	.l = 0x2d,
> +	/* .l includes CAL_L_VAL, L_VAL fields */
> +	.l = 0x0044002d,
>   	.alpha = 0x0,
>   	.config_ctl_val = 0x20485699,
>   	.config_ctl_hi_val = 0x00182261,
> @@ -247,7 +250,8 @@ static struct clk_alpha_pll_postdiv cam_cc_pll3_out_even = {
>   };
>   
>   static const struct alpha_pll_config cam_cc_pll4_config = {
> -	.l = 0x2d,
> +	/* .l includes CAL_L_VAL, L_VAL fields */
> +	.l = 0x0044002d,
>   	.alpha = 0x0,
>   	.config_ctl_val = 0x20485699,
>   	.config_ctl_hi_val = 0x00182261,
> @@ -295,7 +299,8 @@ static struct clk_alpha_pll_postdiv cam_cc_pll4_out_even = {
>   };
>   
>   static const struct alpha_pll_config cam_cc_pll5_config = {
> -	.l = 0x2d,
> +	/* .l includes CAL_L_VAL, L_VAL fields */
> +	.l = 0x0044002d,
>   	.alpha = 0x0,
>   	.config_ctl_val = 0x20485699,
>   	.config_ctl_hi_val = 0x00182261,
> @@ -343,7 +348,8 @@ static struct clk_alpha_pll_postdiv cam_cc_pll5_out_even = {
>   };
>   
>   static const struct alpha_pll_config cam_cc_pll6_config = {
> -	.l = 0x2d,
> +	/* .l includes CAL_L_VAL, L_VAL fields */
> +	.l = 0x0044002d,
>   	.alpha = 0x0,
>   	.config_ctl_val = 0x20485699,
>   	.config_ctl_hi_val = 0x00182261,
> @@ -391,7 +397,8 @@ static struct clk_alpha_pll_postdiv cam_cc_pll6_out_even = {
>   };
>   
>   static const struct alpha_pll_config cam_cc_pll7_config = {
> -	.l = 0x2d,
> +	/* .l includes CAL_L_VAL, L_VAL fields */
> +	.l = 0x0044002d,
>   	.alpha = 0x0,
>   	.config_ctl_val = 0x20485699,
>   	.config_ctl_hi_val = 0x00182261,
> @@ -439,7 +446,8 @@ static struct clk_alpha_pll_postdiv cam_cc_pll7_out_even = {
>   };
>   
>   static const struct alpha_pll_config cam_cc_pll8_config = {
> -	.l = 0x32,
> +	/* .l includes CAL_L_VAL, L_VAL fields */
> +	.l = 0x00440032,
>   	.alpha = 0x0,
>   	.config_ctl_val = 0x20485699,
>   	.config_ctl_hi_val = 0x00182261,
> diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
> index f81c7c561352..68a80395997b 100644
> --- a/drivers/clk/qcom/clk-alpha-pll.c
> +++ b/drivers/clk/qcom/clk-alpha-pll.c
> @@ -270,7 +270,6 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
>   #define LUCID_EVO_PCAL_NOT_DONE		BIT(8)
>   #define LUCID_EVO_ENABLE_VOTE_RUN       BIT(25)
>   #define LUCID_EVO_PLL_L_VAL_MASK        GENMASK(15, 0)
> -#define LUCID_EVO_PLL_CAL_L_VAL_SHIFT	16
>   
>   /* ZONDA PLL specific */
>   #define ZONDA_PLL_OUT_MASK	0xf
> @@ -2084,10 +2083,7 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_zonda_ops);
>   void clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
>   				 const struct alpha_pll_config *config)
>   {
> -	u32 lval = config->l;
> -
> -	lval |= TRION_PLL_CAL_VAL << LUCID_EVO_PLL_CAL_L_VAL_SHIFT;
> -	clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), lval);
> +	clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l);
>   	clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha);
>   	clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);
>   	clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val);
> diff --git a/drivers/clk/qcom/dispcc-sm8450.c b/drivers/clk/qcom/dispcc-sm8450.c
> index adbfd30bfc96..293eae670a23 100644
> --- a/drivers/clk/qcom/dispcc-sm8450.c
> +++ b/drivers/clk/qcom/dispcc-sm8450.c
> @@ -76,7 +76,8 @@ static struct pll_vco lucid_evo_vco[] = {
>   };
>   
>   static const struct alpha_pll_config disp_cc_pll0_config = {
> -	.l = 0xD,
> +	/* .l includes CAL_L_VAL, L_VAL fields */
> +	.l = 0x0044000d,
>   	.alpha = 0x6492,
>   	.config_ctl_val = 0x20485699,
>   	.config_ctl_hi_val = 0x00182261,
> @@ -103,7 +104,8 @@ static struct clk_alpha_pll disp_cc_pll0 = {
>   };
>   
>   static const struct alpha_pll_config disp_cc_pll1_config = {
> -	.l = 0x1F,
> +	/* .l includes CAL_L_VAL, L_VAL fields */
> +	.l = 0x0044001f,
>   	.alpha = 0x4000,
>   	.config_ctl_val = 0x20485699,
>   	.config_ctl_hi_val = 0x00182261,
> diff --git a/drivers/clk/qcom/dispcc-sm8550.c b/drivers/clk/qcom/dispcc-sm8550.c
> index 1e5a11081860..b0d4c623731d 100644
> --- a/drivers/clk/qcom/dispcc-sm8550.c
> +++ b/drivers/clk/qcom/dispcc-sm8550.c
> @@ -76,7 +76,8 @@ static struct pll_vco lucid_ole_vco[] = {
>   };
>   
>   static const struct alpha_pll_config disp_cc_pll0_config = {
> -	.l = 0xd,
> +	/* .l includes RINGOSC_CAL_L_VAL, CAL_L_VAL, L_VAL fields */
> +	.l = 0x4444000d,
>   	.alpha = 0x6492,
>   	.config_ctl_val = 0x20485699,
>   	.config_ctl_hi_val = 0x00182261,
> @@ -103,7 +104,8 @@ static struct clk_alpha_pll disp_cc_pll0 = {
>   };
>   
>   static const struct alpha_pll_config disp_cc_pll1_config = {
> -	.l = 0x1f,
> +	/* .l includes RINGOSC_CAL_L_VAL, CAL_L_VAL, L_VAL fields */
> +	.l = 0x4444001f,
>   	.alpha = 0x4000,
>   	.config_ctl_val = 0x20485699,
>   	.config_ctl_hi_val = 0x00182261,
> diff --git a/drivers/clk/qcom/gpucc-sa8775p.c b/drivers/clk/qcom/gpucc-sa8775p.c
> index 18d23be8d435..153bf6ecb795 100644
> --- a/drivers/clk/qcom/gpucc-sa8775p.c
> +++ b/drivers/clk/qcom/gpucc-sa8775p.c
> @@ -46,7 +46,8 @@ static const struct pll_vco lucid_evo_vco[] = {
>   
>   /* 810MHz configuration */
>   static struct alpha_pll_config gpu_cc_pll0_config = {
> -	.l = 0x2a,
> +	/* .l includes CAL_L_VAL, L_VAL fields */
> +	.l = 0x0044002a,
>   	.alpha = 0x3000,
>   	.config_ctl_val = 0x20485699,
>   	.config_ctl_hi_val = 0x00182261,
> @@ -72,7 +73,8 @@ static struct clk_alpha_pll gpu_cc_pll0 = {
>   
>   /* 1000MHz configuration */
>   static struct alpha_pll_config gpu_cc_pll1_config = {
> -	.l = 0x34,
> +	/* .l includes CAL_L_VAL, L_VAL fields */
> +	.l = 0x00440034,
>   	.alpha = 0x1555,
>   	.config_ctl_val = 0x20485699,
>   	.config_ctl_hi_val = 0x00182261,
> diff --git a/drivers/clk/qcom/gpucc-sm8450.c b/drivers/clk/qcom/gpucc-sm8450.c
> index 16c0381b3087..dddfda880202 100644
> --- a/drivers/clk/qcom/gpucc-sm8450.c
> +++ b/drivers/clk/qcom/gpucc-sm8450.c
> @@ -40,7 +40,8 @@ static struct pll_vco lucid_evo_vco[] = {
>   };
>   
>   static struct alpha_pll_config gpu_cc_pll0_config = {
> -	.l = 0x1d,
> +	/* .l includes CAL_L_VAL, L_VAL fields */
> +	.l = 0x0044001d,
>   	.alpha = 0xb000,
>   	.config_ctl_val = 0x20485699,
>   	.config_ctl_hi_val = 0x00182261,
> @@ -67,7 +68,8 @@ static struct clk_alpha_pll gpu_cc_pll0 = {
>   };
>   
>   static struct alpha_pll_config gpu_cc_pll1_config = {
> -	.l = 0x34,
> +	/* .l includes CAL_L_VAL, L_VAL fields */
> +	.l = 0x00440034,
>   	.alpha = 0x1555,
>   	.config_ctl_val = 0x20485699,
>   	.config_ctl_hi_val = 0x00182261,

--
With best wishes
Dmitry