On 23-06-01 12:42:22, Konrad Dybcio wrote:
>
>
> On 1.06.2023 12:38, Abel Vesa wrote:
> > The USB HC node is missing the interconnect paths, so add them.
> >
> > Fixes: 7f7e5c1b037f ("arm64: dts: qcom: sm8550: Add USB PHYs and controller nodes")
> For context, it's a fix in the context of "we should prooobably have
> this if we want to fix the icc driver to include sync state".
Fair enough...
> > Signed-off-by: Abel Vesa <abel.vesa@xxxxxxxxxx>
> > ---
> Reviewed-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxx>
>
>
>
> sidenote:
>
> on recent SoCs there's also an USB-IPA path:
>
> aggre1_noc MASTER_USB3_0 <-> &config_noc SLAVE_IPA_CFG
AFAIK, support for IPA on SM8550 is not added yet.
We can worry about this 3rd path when IPA support for this platform is
upstreamed.
>
> I don't think we really make use of that upstream today or whether it
> would make enabling IPA necessary (to enable the clocks and reach the
> IPA hardware), but it's something to think about.
>
> Konrad
> > arch/arm64/boot/dts/qcom/sm8550.dtsi | 4 ++++
> > 1 file changed, 4 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> > index 75cd374943eb..4991b2e962d1 100644
> > --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> > @@ -2793,6 +2793,10 @@ usb_1: usb@a6f8800 {
> >
> > resets = <&gcc GCC_USB30_PRIM_BCR>;
> >
> > + interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
> > + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
> > + interconnect-names = "usb-ddr", "apps-usb";
> > +
> > status = "disabled";
> >
> > usb_1_dwc3: usb@a600000 {
