On 5/26/23 17:28, patrick.delaunay@xxxxxxxxxxx wrote:
Hi Marek,
Hi,
From: Marek Vasut <marex@xxxxxxx> Sent: Wednesday, May 17, 2023 5:25 PM Subject: [PATCH v2 3/3] ARM: dts: stm32: Add nvmem-syscon node to TAMP to expose boot count on DHSOM Add nvmem-syscon subnode to expose TAMP_BKPxR register 19 to user space. This register contains U-Boot boot counter, by exposing it to user space the user space can reset the boot counter. Read access example: " $ hexdump -vC /sys/bus/nvmem/devices/5c00a000.tamp\:nvmem0/nvmem 00000000 0c 00 c4 b0 " Signed-off-by: Marek Vasut <marex@xxxxxxx> --- Cc: Alexandre Torgue <alexandre.torgue@xxxxxxxxxxx> Cc: Conor Dooley <conor+dt@xxxxxxxxxx> Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@xxxxxxxxxx> Cc: Marek Vasut <marex@xxxxxxx> Cc: Maxime Coquelin <mcoquelin.stm32@xxxxxxxxx> Cc: Rob Herring <robh+dt@xxxxxxxxxx> Cc: Srinivas Kandagatla <srinivas.kandagatla@xxxxxxxxxx> Cc: devicetree@xxxxxxxxxxxxxxx Cc: kernel@xxxxxxxxxxxxxxxxxx Cc: linux-arm-kernel@xxxxxxxxxxxxxxxxxxx Cc: linux-stm32@xxxxxxxxxxxxxxxxxxxxxxxxxxxx --- V2: No change --- arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi | 11 +++++++++++ arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi | 11 +++++++++++ 2 files changed, 22 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi index 74735552f4803..b2557bb718f52 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi @@ -537,6 +537,17 @@ &sdmmc3 { status = "okay"; }; +&tamp { + #address-cells = <1>; + #size-cells = <1>; + + /* Boot counter */ + nvmem { + compatible = "nvmem-syscon"; + reg = <0x14c 0x4>; + }; +}; + &uart4 { pinctrl-names = "default"; pinctrl-0 = <&uart4_pins_a>; diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi index bba19f21e5277..864960387e634 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi @@ -269,3 +269,14 @@ &rng1 { &rtc { status = "okay"; }; + +&tamp { + #address-cells = <1>; + #size-cells = <1>; + + /* Boot counter */ + nvmem {According binding you need to add "@<reg>" => nvmem@14c And you export only TAMP_BKP19R directly in a nvmem region ?
4 bytes is more than plenty for boot counter , yes.
+ compatible = "nvmem-syscon"; + reg = <0x14c 0x4>; + }; +};the boot counter could be a nvem cell so you could expose other backup registers For example : &tamp { #address-cells = <1>; #size-cells = <1>; nvmem@14c { compatible = "nvmem-syscon"; reg = <0x14c 0x4>; /* Data cells */ boot_counter: boot-counter@14c { reg = <0x14c 0x4>; }; }; }; Even if you export more backup register the cell will be correctly described in DT and could be accessible directly with sysfs without managed offset in userland with https://lore.kernel.org/lkml/202305240724.z3McDuYM-lkp@xxxxxxxxx/T/ Or previous serie https://lore.kernel.org/lkml/20211220064730.28806-1-zajec5@xxxxxxxxx/ for example to export all the free register: Reference: https://wiki.st.com/stm32mpu/wiki/STM32MP15_backup_registers the cell " boot-counter" will be always available for users. &tamp { #address-cells = <1>; #size-cells = <1>; /* backup register: 10 to 21 */ nvmem@0x128 { compatible = "nvmem-syscon"; reg = <0x128 0x44>; /* Data cells */ boot_counter: boot-counter@14c { reg = <0x14c 0x4>; }; boot_mode: boot-mode@150 { reg = <0x150 0x4>; }; .... }; };
Sure, thanks. I'm not sure I understood the message above.
