Hello Lucas,
On Thu, 2 Mar 2023 16:35:25 +0100
Luca Ceresoli <luca.ceresoli@xxxxxxxxxxx> wrote:
> Hello Lucas,
>
> On Fri, 26 Aug 2022 21:29:32 +0200
> Lucas Stach <l.stach@xxxxxxxxxxxxxx> wrote:
>
> > Enable the DT nodes for HDMI TX and PHY and add the pinctrl for the few
> > involved pins that are configurable.
> >
> > Signed-off-by: Lucas Stach <l.stach@xxxxxxxxxxxxxx>
Any updates to these patches? I haven't found any v2 on the list.
> I'm joining late to this party... Is this the latest version of this
> series? I haven't found any more recent, but if it is not the case
> would you point me to the most recent one please?
>
> > + pinctrl_hdmi: hdmigrp {
> > + fsl,pins = <
> > + MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x1c3
> > + MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x1c3
>
> Is the low nibble (0x3) right?BIT(0) is reserved according too the
> reference manual.
>
> Also, all the non-reserved bits in that nibble are bits 1 and 2, which
> set the drive strength. For an I2C line it seems that the minimum drive
> strength (0x0) should be enough for an I2C line: with any drive
> strength setting the supported frequency is >= 65 MHz.
>
> > + MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x19
> > + MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x19
>
> Here as well, bits 0 and 3 are reserved.
About these pinctrls, I am using these settings on the MSC SM2-MB-EP1
board and they appear to be working just as those you are using (but I
haven't tested CEC):
MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x1c2
MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x1c2
MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x10
MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x10
Best regards,
Luca
--
Luca Ceresoli, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
