On 5/22/23 14:51, Fabio Estevam wrote:
From: Fabio Estevam <festevam@xxxxxxx>
The i.MX6SX General Purpose Registers is a set of register that serves
various different purposes and in particular, IOMUXC_GPR_GPR6, at
offset 0x18, can be used to configure the LDB block.
Signed-off-by: Fabio Estevam <festevam@xxxxxxx>
---
Changes since v4:
- Renamed to syscon@20e4000 (Conor).
.../bindings/soc/imx/fsl,imx6sx-gpr.yaml | 84 +++++++++++++++++++
1 file changed, 84 insertions(+)
create mode 100644 Documentation/devicetree/bindings/soc/imx/fsl,imx6sx-gpr.yaml
diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,imx6sx-gpr.yaml b/Documentation/devicetree/bindings/soc/imx/fsl,imx6sx-gpr.yaml
new file mode 100644
index 000000000000..22777ecfb56b
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx6sx-gpr.yaml
@@ -0,0 +1,84 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/imx/fsl,imx6sx-gpr.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP i.MX6SX General Purpose Register
+
+maintainers:
+ - Fabio Estevam <festevam@xxxxxxx>
+
+description:
+ The i.MX6SX General Purpose Registers is a set of register that serves
+ for various purposes and in particular, IOMUXC_GPR_GPR6, at offset 0x18,
+ can be used to configure the LDB block.
+
+properties:
+ compatible:
+ items:
+ - const: fsl,imx6sx-iomuxc-gpr
+ - const: fsl,imx6q-iomuxc-gpr
+ - const: syscon
Take a look at MX6Q and notice how the iomuxc and GPR register sets
share the same base address . That's different on MX6SX where they are
separate. So I think this binding should be specific to MX6SX ONLY and
for MX6Q the subnode probing should be handled in the IOMUXC driver
instead , i.e. drop the fsl,imx6q-iomuxc-gpr here and in imx6sx.dtsi .
$ git grep -A 2 @20e0000 arch/arm/boot/dts/imx6qdl.dtsi
arch/arm/boot/dts/imx6qdl.dtsi: gpr: iomuxc-gpr@20e0000 {
arch/arm/boot/dts/imx6qdl.dtsi- compatible =
"fsl,imx6q-iomuxc-gpr", "syscon", "simple-mfd";
arch/arm/boot/dts/imx6qdl.dtsi- reg = <0x20e0000
0x38>;
--
arch/arm/boot/dts/imx6qdl.dtsi: iomuxc: pinctrl@20e0000 {
arch/arm/boot/dts/imx6qdl.dtsi- compatible =
"fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";
arch/arm/boot/dts/imx6qdl.dtsi- reg = <0x20e0000
0x4000>;
