On 5/20/2023 4:53 PM, Konrad Dybcio wrote:
On 19.05.2023 10:51, Komal Bajaj wrote:
Add sdhc node for eMMC on QDU1000 and QRU1000 SoCs.
Signed-off-by: Komal Bajaj <quic_kbajaj@xxxxxxxxxxx>
---
arch/arm64/boot/dts/qcom/qdu1000.dtsi | 60 +++++++++++++++++++++++++++
1 file changed, 60 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi
index 734438113bba..6113def66a08 100644
--- a/arch/arm64/boot/dts/qcom/qdu1000.dtsi
+++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi
@@ -19,6 +19,10 @@
chosen: chosen { };
+ aliases {
+ mmc0 = &sdhc_1; /*SDC1 eMMC slot*/
+ };
+
cpus {
#address-cells = <2>;
#size-cells = <0>;
@@ -842,6 +846,62 @@
#hwlock-cells = <1>;
};
+ sdhc_1: mmc@8804000 {
+ compatible = "qcom,qdu1000-sdhci", "qcom,sdhci-msm-v5";
+ reg = <0x0 0x08804000 0x0 0x1000>,
+ <0x0 0x08805000 0x0 0x1000>;
+
confusing newline
Will remove it in the next patch set.
+ reg-names = "hc", "cqhci";
+
+ interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hc_irq", "pwr_irq";
+
+ clocks = <&gcc GCC_SDCC5_AHB_CLK>,
+ <&gcc GCC_SDCC5_APPS_CLK>,
SDCC>5<?
These names are used in accordance with the clock hardware.
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "iface", "core", "xo";
Please keep one per line
Noted.
+
+ /* Add dt entry for gcc hw reset */
+ resets = <&gcc GCC_SDCC5_BCR>;
5?
Reason same as above.
+
+ interconnects = <&system_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_SDCC_2 0>;
+ interconnect-names = "sdhc-ddr", "cpu-sdhc";
+ power-domains = <&rpmhpd QDU1000_CX>;
+ operating-points-v2 = <&sdhc1_opp_table>;
+
+ iommus = <&apps_smmu 0x0080 0x0>;
Please remove the leading zeroes from the stream id
Sure, will do so.
+ dma-coherent;
+
+ bus-width = <8>;
----
+ non-removable;
+ supports-cqe;
+
+ no-sd;
+ no-sdio;
+
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ mmc-hs400-1_8v;
+ mmc-hs400-enhanced-strobe;
+ cap-mmc-hw-reset;
----
This bit is board-specific
Okay, will move these bits to board specific file.
+
+ qcom,dll-config = <0x0007642c>;
+ qcom,ddr-config = <0x80040868>;
+
+ status = "disabled";
+
+ sdhc1_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-384000000 {
+ opp-hz = /bits/ 64 <384000000>;
+ required-opps = <&rpmhpd_opp_min_svs>;
You added interconnects, but not any opp-peak-kBps / opp-avg-kBps,
presumably mistakengly?
Also, 384Mhz + min_svs sounds a bit weird? Is that the correct
level for this SoC?
Yes, you are right, this is wrong configuration, will correct it in the
next patch set.
Thanks
Komal
Konrad
+ };
+ };
+ };
+
pdc: interrupt-controller@b220000 {
compatible = "qcom,qdu1000-pdc", "qcom,pdc";
reg = <0x0 0xb220000 0x0 0x30000>, <0x0 0x174000f0 0x0 0x64>;
--
2.17.1
