On 5/15/23 2:02 AM, Achal Verma wrote:
From: Matt Ranostay <mranostay@xxxxxx> J784S4 SoC supports two PCIE instances as follows: * PCIE0 - 4x lanes * PCIE1 - 4x lanes J784S4 EVM board has the following PCIE connectors: * PCIE0 - 4x lanes * PCIE1 - 2x lanes Signed-off-by: Matt Ranostay <mranostay@xxxxxx> Signed-off-by: Siddharth Vadapalli <s-vadapalli@xxxxxx> Signed-off-by: Achal Verma <a-verma1@xxxxxx> --- This patch depends on: https://lore.kernel.org/all/20230310111630.743023-1-s-vadapalli@xxxxxx/ https://lore.kernel.org/all/20230425131607.290707-1-j-choudhary@xxxxxx/ https://lore.kernel.org/all/20230401112633.2406604-1-a-verma1@xxxxxx/ arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 65 +++++++++++ arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 126 +++++++++++++++++++++
I would split this into two patches, first add the nodes to the MAIN domain dtsi file. Then after enable the SerDes and PCIe nodes for the EVM board. Also, drop the pcie0_ep nodes, reasoning here: https://lore.kernel.org/lkml/20230515172137.474626-2-afd@xxxxxx/ Andrew
