On Thu, May 18, 2023 at 10:31:35PM -0500, Samuel Holland wrote: > Hi Jisheng, DT maintainers, Sick, thanks for piping up Samuel! Both Rob and Krzysztof are not around at the moment, so that probably leaves it up to me.. I'm adding Arnd in case he has a take here too. > On 5/18/23 10:22, Jisheng Zhang wrote: > > Several SoMs and boards are available that feature the Bouffalolab > > bl808 SoC. Document the compatible strings. > > > > Signed-off-by: Jisheng Zhang <jszhang@xxxxxxxxxx> > > Acked-by: Palmer Dabbelt <palmer@xxxxxxxxxxxx> > > Reviewed-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx> > > --- > > .../bindings/riscv/bouffalolab.yaml | 29 +++++++++++++++++++ > > 1 file changed, 29 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/riscv/bouffalolab.yaml > > > > diff --git a/Documentation/devicetree/bindings/riscv/bouffalolab.yaml b/Documentation/devicetree/bindings/riscv/bouffalolab.yaml > > new file mode 100644 > > index 000000000000..3b25d1a5d04a > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/riscv/bouffalolab.yaml > > @@ -0,0 +1,29 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/riscv/bouffalolab.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Bouffalo Lab Technology SoC-based boards > > + > > +maintainers: > > + - Jisheng Zhang <jszhang@xxxxxxxxxx> > > + > > +description: > > + Bouffalo Lab Technology SoC-based boards > > + > > +properties: > > + $nodename: > > + const: '/' > > + compatible: > > + oneOf: > > + - description: Carrier boards for the Sipeed M1s SoM > > + items: > > + - enum: > > + - sipeed,m1s-dock > > + - const: sipeed,m1s > > + - const: bouffalolab,bl808 > > As mentioned in the message for patch 5, "The Bouffalolab bl808 SoC > contains three riscv CPUs, namely M0, D0 and LP. The D0 is 64bit RISC-V > GC compatible, so can run linux." > > I have also been running U-Boot and NOMMU Linux on the less powerful, > but still quite fast, "M0" core. However, this core needs a different > DTB because: > 1) The CPU is different (T-HEAD E907 instead of C906). > 2) The interrupt routing is completely different. > a. The M0 core contains a CLIC instead of a PLIC. > b. The peripherals in the SoC are split between two buses. Those > on one bus have their IRQs directly connected to M0, and share > a multiplexed IRQ connection to D0; and vice versa for the > other bus. So each bus's interrupt-parent needs to be swapped. > > Using some preprocessor magic like we did for Allwinner and Renesas, I > was able to share most of the SoC and board DTs between the cores[1]. > However, this still ends up with two DTs for each board. So here are my > questions: > - Is this acceptable? I expected it to look worse than it actually turned out to be. I don't think Krzysztof in particular is a fan of having conditional bits in dts files, but for the shared arm/riscv stuff there was not really another sensible option. > - Is there precedent for how we should name the two board DTs? Arnd might have some idea about precedent here, but I like your naming well enough. > - How does this affect the board and SoC compatible strings? > - Should there be a separate "bouffalolab,bl808-d0" in addition to > "bouffalolab,bl808"? What ordering were you intending here? "pine64,0x64" "bouffalolab,bl808" "bouffalolab,bl808-d0"? That doesn't really seem correct though, as it does not get less specific as you move right. "pine64,0x64" "bouffalolab,bl808-d0" "bouffalolab,bl808" doesn't seem right either though, for the same sort of reason. > - Is it acceptable to use the same board compatible string for both, > since the _board_ part of the DT does not change, only things > inside the SoC? I think you may need to have 2 compatibles per board, depending on which cpu. Perhaps even as verbose as: "pine61,0x64-d0" "pine64,0x64" "bouffalolab,bl808-d0" "bouffalolab,bl808" Not exactly straightforward though, is it! > It would be possible to avoid having two DTs per board by guarding all > of the differences behind "#ifdef CONFIG_64BIT", but that seems wrong > because you would end up with two totally incompatible DTBs named the > same thing, depending on how the DTB was built. I think having 2 dtbs is fine, and as I mentioned, I've seen Krzysztof complain previously about conditional bits like that. Cheers, Conor.
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