PCIe nodes defined in the top-level J721e SoC dtsi files are incomplete
and will not be functional unless they are extended with a SerDes PHY.
And usually only one of the two modes can be used at a time as they
share a SerDes link.
As the PHY and mode is only known at the board integration level, these
nodes should only be enabled when provided with this information.
Disable the PCIe nodes in the dtsi files and only enable the ones that
are actually pinned out on a given board.
Signed-off-by: Andrew Davis <afd@xxxxxx>
---
.../boot/dts/ti/k3-j721e-beagleboneai64.dts | 16 +---------------
.../boot/dts/ti/k3-j721e-common-proc-board.dts | 7 +++----
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 4 ++++
arch/arm64/boot/dts/ti/k3-j721e-sk.dts | 12 ++----------
4 files changed, 10 insertions(+), 29 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts
index d77eeff0d81d..be0c5431119e 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts
@@ -872,12 +872,8 @@ serdes1_pcie_link: phy@0 {
};
};
-&pcie0_rc {
- /* Unused */
- status = "disabled";
-};
-
&pcie1_rc {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pcie1_rst_pins_default>;
phys = <&serdes1_pcie_link>;
@@ -887,16 +883,6 @@ &pcie1_rc {
reset-gpios = <&main_gpio0 22 GPIO_ACTIVE_HIGH>;
};
-&pcie2_rc {
- /* Unused */
- status = "disabled";
-};
-
-&pcie3_rc {
- /* Unused */
- status = "disabled";
-};
-
&icssg0_mdio {
/* Unused */
status = "disabled";
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
index 87b7263f6547..975a5161eb96 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
@@ -820,6 +820,7 @@ &mhdp {
};
&pcie0_rc {
+ status = "okay";
reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>;
phys = <&serdes0_pcie_link>;
phy-names = "pcie-phy";
@@ -827,6 +828,7 @@ &pcie0_rc {
};
&pcie1_rc {
+ status = "okay";
reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>;
phys = <&serdes1_pcie_link>;
phy-names = "pcie-phy";
@@ -834,16 +836,13 @@ &pcie1_rc {
};
&pcie2_rc {
+ status = "okay";
reset-gpios = <&exp2 20 GPIO_ACTIVE_HIGH>;
phys = <&serdes2_pcie_link>;
phy-names = "pcie-phy";
num-lanes = <2>;
};
-&pcie3_rc {
- status = "disabled";
-};
-
&icssg0_mdio {
status = "disabled";
};
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
index e39f6d1e8d40..18f4661d37bf 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
@@ -814,6 +814,7 @@ pcie0_rc: pcie@2900000 {
ranges = <0x01000000 0x0 0x10001000 0x0 0x10001000 0x0 0x0010000>,
<0x02000000 0x0 0x10011000 0x0 0x10011000 0x0 0x7fef000>;
dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
+ status = "disabled";
};
pcie1_rc: pcie@2910000 {
@@ -842,6 +843,7 @@ pcie1_rc: pcie@2910000 {
ranges = <0x01000000 0x0 0x18001000 0x0 0x18001000 0x0 0x0010000>,
<0x02000000 0x0 0x18011000 0x0 0x18011000 0x0 0x7fef000>;
dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
+ status = "disabled";
};
pcie2_rc: pcie@2920000 {
@@ -870,6 +872,7 @@ pcie2_rc: pcie@2920000 {
ranges = <0x01000000 0x0 0x00001000 0x44 0x00001000 0x0 0x0010000>,
<0x02000000 0x0 0x00011000 0x44 0x00011000 0x0 0x7fef000>;
dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
+ status = "disabled";
};
pcie3_rc: pcie@2930000 {
@@ -898,6 +901,7 @@ pcie3_rc: pcie@2930000 {
ranges = <0x01000000 0x0 0x00001000 0x44 0x10001000 0x0 0x0010000>,
<0x02000000 0x0 0x00011000 0x44 0x10011000 0x0 0x7fef000>;
dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
+ status = "disabled";
};
serdes_wiz4: wiz@5050000 {
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts
index 07d3282a583b..66a8559b3755 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts
@@ -872,6 +872,7 @@ serdes1_pcie_link: phy@0 {
};
&pcie0_rc {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&ekey_reset_pins_default>;
reset-gpios = <&main_gpio0 72 GPIO_ACTIVE_HIGH>;
@@ -882,6 +883,7 @@ &pcie0_rc {
};
&pcie1_rc {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mkey_reset_pins_default>;
reset-gpios = <&wkup_gpio0 11 GPIO_ACTIVE_HIGH>;
@@ -891,16 +893,6 @@ &pcie1_rc {
num-lanes = <2>;
};
-&pcie2_rc {
- /* Unused */
- status = "disabled";
-};
-
-&pcie3_rc {
- /* Unused */
- status = "disabled";
-};
-
&icssg0_mdio {
status = "disabled";
};
--
2.39.2
