Dne sreda, 10. maj 2023 ob 10:11:10 CEST je Maksim Kiselev napisal(a): > Previously SPI controllers in Allwinner SoCs has a clock divider inside. > However now the clock divider is removed and to set the transfer clock > rate it's only needed to set the SPI module clock to the target value > and configure a proper work mode. > > According to the datasheet there are three work modes: > | SPI Sample Mode | SDM(bit13) | SDC(bit11) | Run Clock | > | > |-------------------------|------------|------------|-----------| > | > | normal sample | 1 | 0 | <= 24 MHz | > | delay half cycle sample | 0 | 0 | <= 40 MHz | > | delay one cycle sample | 0 | 1 | >= 80 MHz | > > Add a quirk for this kind of SPI controllers. > > Co-developed-by: Icenowy Zheng <icenowy@xxxxxxx> > Signed-off-by: Maksim Kiselev <bigunclemax@xxxxxxxxx> Reviewed-by: Jernej Skrabec <jernej.skrabec@xxxxxxxxx> Best regards, Jernej
