On 2023/5/6 14:31, Krzysztof Kozlowski wrote:
> On 06/05/2023 03:45, Changhuang Liang wrote:
>>
>> Hi, Krzysztof and Conor
>>
>> Due to the current aon pmu needs to be adjusted, it affects the syscon in PLL series.
>> So It's inevitable to change syscon in PLL series.
>>
>> My current idea is PLL series don't add the aon_syscon node. I will add it in my
>> aon pmu series in next version like this:
>>
>> aon_syscon: syscon@17010000 {
>> compatible = "starfive,jh7110-aon-pmu", "syscon";
>> reg = <0x0 0x17010000 0x0 0x1000>;
>> #power-domain-cells = <1>;
>> };
>>
>> In my opinion, the first we add "starfive,jh7110-aon-syscon" because "syscon" can
>> not appear alone in the compatible. If we have "starfive,jh7110-aon-pmu", this
>> "starfive,jh7110-aon-syscon" is not a must-be need.
>>
>> Do you agree with doing so.
>
> Sorry guys, I don't know what you talk about. I have no clue what are
> PLL and aon series. More over I don't understand what is complicated
> here... all SoCs follow the same rules and similar way of development.
>
In other words, if I use the above approach,
[1] https://lore.kernel.org/all/20230414024157.53203-6-xingyu.wu@xxxxxxxxxxxxxxxx/
[2] https://lore.kernel.org/all/20230414024157.53203-7-xingyu.wu@xxxxxxxxxxxxxxxx/
Links [1][2] need to be dropped "aon_syscon" node.
