Re: [PATCH 1/7] dt-bindings: phy: qcom,sc8280xp-qmp-usb43dp: Add ports and orientation-switch

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

 



On 27/04/2023 21:52, Bjorn Andersson wrote:
On Wed, Apr 26, 2023 at 11:21:29AM +0100, Bryan O'Donoghue wrote:
On Tue, Apr 25, 2023 at 4:40 AM Bjorn Andersson
<quic_bjorande@xxxxxxxxxxx> wrote:

The QMP combo phy can be connected to a TCPM, a USB controller and a
DisplayPort controller for handling USB Type-C orientation switching
and propagating HPD signals.

Extend the binding to allow these connections to be described.

Signed-off-by: Bjorn Andersson <quic_bjorande@xxxxxxxxxxx>
---
  .../phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml    | 51 +++++++++++++++++++
  1 file changed, 51 insertions(+)

diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml
index 3cd5fc3e8fab..c037ac90ce7f 100644
--- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml
@@ -60,6 +60,26 @@ properties:
      description:
        See include/dt-bindings/dt-bindings/phy/phy-qcom-qmp.h

+  orientation-switch:
+    description:
+      Flag the PHY as possible handler of USB Type-C orientation switching
+    type: boolean
+
+  ports:
+    $ref: /schemas/graph.yaml#/properties/ports
+    properties:
+      port@0:
+        $ref: /schemas/graph.yaml#/properties/port
+        description: Output endpoint of the PHY
+
+      port@1:
+        $ref: /schemas/graph.yaml#/$defs/port-base
+        description: Incoming endpoint from the USB controller

Do you really need this one ?

The controller doesn't process orientation switching.


I don't have a need for it, as we can deal with role switching by
connecting connector/port@0 to the dwc3.

But if we ever have a need to describe the dwc3 -> QMP -> connector path
in the of_graph I think it would look prettier to have USB input as
port@1 and DP input as port@2...

I think it would be great to have port@1 for USB SS and port@2 for DP,
otherwise we need to add 2 endpoints as I sent in
https://lore.kernel.org/all/20230503-topic-sm8450-graphics-dp-next-v1-1-d1ee9397f2a6@xxxxxxxxxx/
since we split USB HS and SS streams on SM8[345]50 platforms.


Do you have a concern with keeping it around in the DT (the
implementation doesn't need to care)?

Regards,
Bjorn




[Index of Archives]     [Device Tree Compilter]     [Device Tree Spec]     [Linux Driver Backports]     [Video for Linux]     [Linux USB Devel]     [Linux PCI Devel]     [Linux Audio Users]     [Linux Kernel]     [Linux SCSI]     [XFree86]     [Yosemite Backpacking]


  Powered by Linux