Add SM6115 / SM4250 SoC EUD support in qcom_eud driver.
On some SoCs (like the SM6115 / SM4250 SoC), the mode manager
needs to be accessed only via the secure world (through 'scm'
calls).
Also, the enable bit inside 'tcsr_check_reg' needs to be set
first to set the eud in 'enable' mode on these SoCs.
Since this difference comes from how the firmware is configured, so
the driver now relies on the presence of an extra boolean DT property
to identify if secure access is needed.
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@xxxxxxxxxx>
---
drivers/usb/misc/Kconfig | 1 +
drivers/usb/misc/qcom_eud.c | 66 ++++++++++++++++++++++++++++++++++---
2 files changed, 62 insertions(+), 5 deletions(-)
diff --git a/drivers/usb/misc/Kconfig b/drivers/usb/misc/Kconfig
index 99b15b77dfd5..fe1b5fec1dfc 100644
--- a/drivers/usb/misc/Kconfig
+++ b/drivers/usb/misc/Kconfig
@@ -147,6 +147,7 @@ config USB_APPLEDISPLAY
config USB_QCOM_EUD
tristate "QCOM Embedded USB Debugger(EUD) Driver"
depends on ARCH_QCOM || COMPILE_TEST
+ select QCOM_SCM
select USB_ROLE_SWITCH
help
This module enables support for Qualcomm Technologies, Inc.
diff --git a/drivers/usb/misc/qcom_eud.c b/drivers/usb/misc/qcom_eud.c
index b7f13df00764..b4736edcc64c 100644
--- a/drivers/usb/misc/qcom_eud.c
+++ b/drivers/usb/misc/qcom_eud.c
@@ -5,12 +5,14 @@
#include <linux/bitops.h>
#include <linux/err.h>
+#include <linux/firmware/qcom/qcom_scm.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
+#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/sysfs.h>
@@ -30,15 +32,22 @@
#define EUD_INT_SAFE_MODE BIT(4)
#define EUD_INT_ALL (EUD_INT_VBUS | EUD_INT_SAFE_MODE)
+struct eud_soc_cfg {
+ u32 tcsr_check_offset;
+};
+
struct eud_chip {
struct device *dev;
struct usb_role_switch *role_sw;
+ const struct eud_soc_cfg *eud_cfg;
void __iomem *base;
void __iomem *mode_mgr;
unsigned int int_status;
int irq;
bool enabled;
bool usb_attached;
+ bool secure_mode_enable;
+ phys_addr_t secure_mode_mgr;
};
static int enable_eud(struct eud_chip *priv)
@@ -46,7 +55,11 @@ static int enable_eud(struct eud_chip *priv)
writel(EUD_ENABLE, priv->base + EUD_REG_CSR_EUD_EN);
writel(EUD_INT_VBUS | EUD_INT_SAFE_MODE,
priv->base + EUD_REG_INT1_EN_MASK);
- writel(1, priv->mode_mgr + EUD_REG_EUD_EN2);
+
+ if (priv->secure_mode_mgr)
+ qcom_scm_io_writel(priv->secure_mode_mgr + EUD_REG_EUD_EN2, BIT(0));
+ else
+ writel(1, priv->mode_mgr + EUD_REG_EUD_EN2);
return usb_role_switch_set_role(priv->role_sw, USB_ROLE_DEVICE);
}
@@ -54,7 +67,11 @@ static int enable_eud(struct eud_chip *priv)
static void disable_eud(struct eud_chip *priv)
{
writel(0, priv->base + EUD_REG_CSR_EUD_EN);
- writel(0, priv->mode_mgr + EUD_REG_EUD_EN2);
+
+ if (priv->secure_mode_mgr)
+ qcom_scm_io_writel(priv->secure_mode_mgr + EUD_REG_EUD_EN2, 0);
+ else
+ writel(0, priv->mode_mgr + EUD_REG_EUD_EN2);
}
static ssize_t enable_show(struct device *dev,
@@ -178,12 +195,15 @@ static void eud_role_switch_release(void *data)
static int eud_probe(struct platform_device *pdev)
{
struct eud_chip *chip;
+ struct resource *res;
+ phys_addr_t tcsr_base, tcsr_check;
int ret;
chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
if (!chip)
return -ENOMEM;
+
chip->dev = &pdev->dev;
chip->role_sw = usb_role_switch_get(&pdev->dev);
@@ -200,9 +220,40 @@ static int eud_probe(struct platform_device *pdev)
if (IS_ERR(chip->base))
return PTR_ERR(chip->base);
- chip->mode_mgr = devm_platform_ioremap_resource(pdev, 1);
- if (IS_ERR(chip->mode_mgr))
- return PTR_ERR(chip->mode_mgr);
+ chip->secure_mode_enable = of_property_read_bool(chip->dev->of_node,
+ "qcom,secure-mode-enable");
+ /*
+ * EUD block on a few Qualcomm SoCs need secure register access.
+ * Check for the same.
+ */
+ if (chip->secure_mode_enable) {
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+ if (!res)
+ return dev_err_probe(chip->dev, -ENODEV,
+ "failed to get secure_mode_mgr reg base\n");
+
+ chip->secure_mode_mgr = res->start;
+ } else {
+ chip->mode_mgr = devm_platform_ioremap_resource(pdev, 1);
+ if (IS_ERR(chip->mode_mgr))
+ return PTR_ERR(chip->mode_mgr);
+ }
+
+ /* Check for any SoC specific config data */
+ chip->eud_cfg = of_device_get_match_data(&pdev->dev);
+ if (chip->eud_cfg) {
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
+ if (!res)
+ return dev_err_probe(chip->dev, -ENODEV,
+ "failed to get tcsr reg base\n");
+
+ tcsr_base = res->start;
+ tcsr_check = tcsr_base + chip->eud_cfg->tcsr_check_offset;
+
+ ret = qcom_scm_io_writel(tcsr_check, BIT(0));
+ if (ret)
+ return dev_err_probe(chip->dev, ret, "failed to write tcsr check reg\n");
+ }
chip->irq = platform_get_irq(pdev, 0);
ret = devm_request_threaded_irq(&pdev->dev, chip->irq, handle_eud_irq,
@@ -230,8 +281,13 @@ static int eud_remove(struct platform_device *pdev)
return 0;
}
+static const struct eud_soc_cfg sm6115_eud_cfg = {
+ .tcsr_check_offset = 0x25018,
+};
+
static const struct of_device_id eud_dt_match[] = {
{ .compatible = "qcom,sc7280-eud" },
+ { .compatible = "qcom,sm6115-eud", .data = &sm6115_eud_cfg },
{ }
};
MODULE_DEVICE_TABLE(of, eud_dt_match);
--
2.38.1
