Am Montag, 1. Mai 2023, 10:43:53 CEST schrieb Cristian Ciocaltea:
> Convert the Rockchip OTP memory bindings to dt-schema.
>
> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@xxxxxxxxxxxxx>
Reviewed-by: Heiko Stuebner <heiko@xxxxxxxxx>
> ---
> .../bindings/nvmem/rockchip-otp.txt | 25 ------
> .../bindings/nvmem/rockchip-otp.yaml | 83 +++++++++++++++++++
> 2 files changed, 83 insertions(+), 25 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/nvmem/rockchip-otp.txt
> create mode 100644 Documentation/devicetree/bindings/nvmem/rockchip-otp.yaml
>
> diff --git a/Documentation/devicetree/bindings/nvmem/rockchip-otp.txt b/Documentation/devicetree/bindings/nvmem/rockchip-otp.txt
> deleted file mode 100644
> index 40f649f7c2e5..000000000000
> --- a/Documentation/devicetree/bindings/nvmem/rockchip-otp.txt
> +++ /dev/null
> @@ -1,25 +0,0 @@
> -Rockchip internal OTP (One Time Programmable) memory device tree bindings
> -
> -Required properties:
> -- compatible: Should be one of the following.
> - - "rockchip,px30-otp" - for PX30 SoCs.
> - - "rockchip,rk3308-otp" - for RK3308 SoCs.
> -- reg: Should contain the registers location and size
> -- clocks: Must contain an entry for each entry in clock-names.
> -- clock-names: Should be "otp", "apb_pclk" and "phy".
> -- resets: Must contain an entry for each entry in reset-names.
> - See ../../reset/reset.txt for details.
> -- reset-names: Should be "phy".
> -
> -See nvmem.txt for more information.
> -
> -Example:
> - otp: otp@ff290000 {
> - compatible = "rockchip,px30-otp";
> - reg = <0x0 0xff290000 0x0 0x4000>;
> - #address-cells = <1>;
> - #size-cells = <1>;
> - clocks = <&cru SCLK_OTP_USR>, <&cru PCLK_OTP_NS>,
> - <&cru PCLK_OTP_PHY>;
> - clock-names = "otp", "apb_pclk", "phy";
> - };
> diff --git a/Documentation/devicetree/bindings/nvmem/rockchip-otp.yaml b/Documentation/devicetree/bindings/nvmem/rockchip-otp.yaml
> new file mode 100644
> index 000000000000..658ceed14ee2
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/nvmem/rockchip-otp.yaml
> @@ -0,0 +1,83 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/nvmem/rockchip-otp.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Rockchip internal OTP (One Time Programmable) memory
> +
> +maintainers:
> + - Heiko Stuebner <heiko@xxxxxxxxx>
> +
> +allOf:
> + - $ref: nvmem.yaml#
> +
> +properties:
> + compatible:
> + enum:
> + - rockchip,px30-otp
> + - rockchip,rk3308-otp
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + minItems: 3
> + maxItems: 3
> +
> + clock-names:
> + items:
> + - const: otp
> + - const: apb_pclk
> + - const: phy
> +
> + resets:
> + maxItems: 1
> +
> + reset-names:
> + items:
> + - const: phy
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> + - clock-names
> + - resets
> + - reset-names
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/px30-cru.h>
> +
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + otp: efuse@ff290000 {
> + compatible = "rockchip,px30-otp";
> + reg = <0x0 0xff290000 0x0 0x4000>;
> + clocks = <&cru SCLK_OTP_USR>, <&cru PCLK_OTP_NS>,
> + <&cru PCLK_OTP_PHY>;
> + clock-names = "otp", "apb_pclk", "phy";
> + resets = <&cru SRST_OTP_PHY>;
> + reset-names = "phy";
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + cpu_id: id@7 {
> + reg = <0x07 0x10>;
> + };
> +
> + cpu_leakage: cpu-leakage@17 {
> + reg = <0x17 0x1>;
> + };
> +
> + performance: performance@1e {
> + reg = <0x1e 0x1>;
> + bits = <4 3>;
> + };
> + };
> + };
>
