On Thu, Apr 27, 2023 at 07:50:30AM +0200, Dominic Rath wrote: > From: Alexander Bahle <bahle@xxxxxxxxxxxxxxx> > > Add "tx-phy-latency-ps" and "rx-phy-latency-ps" DT bindings for > setting the PCIe PHY latencies. > The properties expect a list of uint32 PHY latencies in picoseconds for > every supported speed starting at PCIe Gen1, e.g.: > > tx-phy-latency-ps = <100000 200000>; /* Gen1: 100ns, Gen2: 200ns */ > rx-phy-latency-ps = <150000 250000>; /* Gen1: 150ns, Gen2: 250ns */ Are these things that could/should be described in a more generic place? They don't look necessarily Cadence-specific. Bjorn
