Update the size of GICC and GICV regions to 8kB as the GICC_DIR & GICV_DIR
registers lie in the second 4kB region. Also, add target CPU encoding.
Fixes: 97cb36ff52a1 ("arm64: dts: qcom: Add ipq9574 SoC and AL02 board support")
Signed-off-by: Devi Priya <quic_devipriy@xxxxxxxxxxx>
---
Changes in V3:
- Split the intc changes to a separate patch and added Fixes tag.
arch/arm64/boot/dts/qcom/ipq9574.dtsi | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
index 3bb7435f5e7f..7e0a16d490f9 100644
--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
@@ -172,14 +172,14 @@
intc: interrupt-controller@b000000 {
compatible = "qcom,msm-qgic2";
reg = <0x0b000000 0x1000>, /* GICD */
- <0x0b002000 0x1000>, /* GICC */
+ <0x0b002000 0x2000>, /* GICC */
<0x0b001000 0x1000>, /* GICH */
- <0x0b004000 0x1000>; /* GICV */
+ <0x0b004000 0x2000>; /* GICV */
#address-cells = <1>;
#size-cells = <1>;
interrupt-controller;
#interrupt-cells = <3>;
- interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
ranges = <0 0x0b00c000 0x3000>;
v2m0: v2m@0 {
--
2.17.1
